[Commit-gnuradio] r10301 - gnuradio/branches/developers/pcreekmore/quantization/usrp/fpga/sdr_lib

[pcreekmore]

Author: pcreekmore
Date: 2009-01-25 15:19:08 -0700 (Sun, 25 Jan 2009)
New Revision: 10301

Modified:
   
gnuradio/branches/developers/pcreekmore/quantization/usrp/fpga/sdr_lib/rx_buffer.v
Log:
Added rx input buffers and 'read phase' counter in preparation for new 
quantization options.

Modified: 
gnuradio/branches/developers/pcreekmore/quantization/usrp/fpga/sdr_lib/rx_buffer.v
===================================================================
--- 
gnuradio/branches/developers/pcreekmore/quantization/usrp/fpga/sdr_lib/rx_buffer.v
  2009-01-25 17:28:58 UTC (rev 10300)
+++ 
gnuradio/branches/developers/pcreekmore/quantization/usrp/fpga/sdr_lib/rx_buffer.v
  2009-01-25 22:19:08 UTC (rev 10301)
@@ -104,26 +104,62 @@
        .aclr ( reset ) );
 
    // DSP Write Side of FIFO
-   reg [15:0] ch_0_reg;
-   reg [15:0] ch_1_reg;
-   reg [15:0] ch_2_reg;
-   reg [15:0] ch_3_reg;
-   reg [15:0] ch_4_reg;
-   reg [15:0] ch_5_reg;
-   reg [15:0] ch_6_reg;
-   reg [15:0] ch_7_reg;
+   reg [15:0] ch_0_buff0, ch_0_buff1, ch_0_buff2, ch_0_buff3, ch_0_buff4;
+   reg [15:0] ch_0_buff5, ch_0_buff6, ch_0_buff7;
+   reg [15:0] ch_1_buff0, ch_1_buff1, ch_1_buff2, ch_1_buff3, ch_1_buff4;
+   reg [15:0] ch_1_buff5, ch_1_buff6, ch_1_buff7;
+   reg [15:0] ch_2_buff0, ch_2_buff1, ch_2_buff2, ch_2_buff3;
+   reg [15:0] ch_3_buff0, ch_3_buff1, ch_3_buff2, ch_3_buff3;
+   reg [15:0] ch_4_buff0, ch_4_buff1, ch_4_buff2;
+   reg [15:0] ch_5_buff0, ch_5_buff1, ch_5_buff2;
+   reg [15:0] ch_6_buff0, ch_6_buff1;
+   reg [15:0] ch_7_buff0, ch_7_buff1;
 
+   // Input buffers
    always @(posedge rxclk)
      if (rxstrobe)
        begin
-         ch_0_reg <= ch_0;
-         ch_1_reg <= ch_1;
-         ch_2_reg <= ch_2;
-         ch_3_reg <= ch_3;
-         ch_4_reg <= ch_4;
-         ch_5_reg <= ch_5;
-         ch_6_reg <= ch_6;
-         ch_7_reg <= ch_7;
+         ch_0_buff0 <= ch_0;
+         ch_0_buff1 <= ch_0_buff0;
+         ch_0_buff2 <= ch_0_buff1;
+         ch_0_buff3 <= ch_0_buff2;
+         ch_0_buff4 <= ch_0_buff3;
+         ch_0_buff5 <= ch_0_buff4;
+         ch_0_buff6 <= ch_0_buff5;
+         ch_0_buff7 <= ch_0_buff6;
+
+         ch_1_buff0 <= ch_1;
+         ch_1_buff1 <= ch_1_buff0;
+         ch_1_buff2 <= ch_1_buff1;
+         ch_1_buff3 <= ch_1_buff2;
+         ch_1_buff4 <= ch_1_buff3;
+         ch_1_buff5 <= ch_1_buff4;
+         ch_1_buff6 <= ch_1_buff5;
+         ch_1_buff7 <= ch_1_buff6;
+
+         ch_2_buff0 <= ch_2;
+         ch_2_buff1 <= ch_2_buff0;
+         ch_2_buff2 <= ch_2_buff1;
+         ch_2_buff3 <= ch_2_buff2;
+
+         ch_3_buff0 <= ch_3;
+         ch_3_buff1 <= ch_3_buff0;
+         ch_3_buff2 <= ch_3_buff1;
+         ch_3_buff3 <= ch_3_buff2;
+
+         ch_4_buff0 <= ch_4;
+         ch_4_buff1 <= ch_4_buff0;
+         ch_4_buff2 <= ch_4_buff1;
+
+         ch_5_buff0 <= ch_5;
+         ch_5_buff1 <= ch_5_buff0;
+         ch_5_buff2 <= ch_5_buff1;
+
+         ch_6_buff0 <= ch_6;
+         ch_6_buff1 <= ch_6_buff0;
+         
+         ch_7_buff0 <= ch_7;
+         ch_7_buff1 <= ch_7_buff0;
        end
 
    // buffer store event counter
@@ -139,15 +175,12 @@
      else
        buffstore_count <= buffstore_count;
 
-   // read phase counter to keep track of 6-channel cases
-   reg [1:0] read_phase;
-   
 
    // Logic to determine if a sufficient number of new samples has been read
    // into the buffers in order to write a full 16-bit word to the output fifo
    reg buffs_ready;
    always @*
-     if (bitwidth==5'd16 || bitwidth==5'd8 && buffstore_count == 4'd1)
+     if (bitwidth == 5'd16 || bitwidth == 5'd8 && buffstore_count == 4'd1)
        buffs_ready <= 1;
      else if (channels == 4'd2)
        case(bitwidth)
@@ -192,6 +225,21 @@
      else
        buffs_ready <= 0;
 
+   // "read phase" counter to keep track of 6-channel cases
+   // Note: could easily change this to only increment for the 6-channel case 
if necessary
+   reg [1:0] read_phase;
+   always @(posedge buffs_ready)
+     if (reset)
+       read_phase <= 2'd0;
+     else
+       case(bitwidth)
+         5'd4 : if (read_phase == 2) read_phase <= 1; else read_phase <= 
read_phase+1;
+         5'd2 : if (read_phase == 3) read_phase <= 1; else read_phase <= 
read_phase+1;
+         5'd1 : if (read_phase == 3) read_phase <= 1; else read_phase <= 
read_phase+1;
+         default : read_phase <= 1;
+       endcase
+
+   // "write phase" counter to keep track of cases with multiple fifo writes 
per rxstrobe
    reg [3:0] phase;
    always @(posedge rxclk)
      if(reset)
@@ -221,20 +269,20 @@
    always @*
      case(phase)
        4'd1 : begin
-         bottom = ch_0_reg;
-         top = ch_1_reg;
+         bottom = ch_0_buff0;
+         top = ch_1_buff0;
        end
        4'd2 : begin
-         bottom = ch_2_reg;
-         top = ch_3_reg;
+         bottom = ch_2_buff0;
+         top = ch_3_buff0;
        end
        4'd3 : begin
-         bottom = ch_4_reg;
-         top = ch_5_reg;
+         bottom = ch_4_buff0;
+         top = ch_5_buff0;
        end
        4'd4 : begin
-         bottom = ch_6_reg;
-         top = ch_7_reg;
+         bottom = ch_6_buff0;
+         top = ch_7_buff0;
        end
        default : begin
          top = 16'hFFFF;
@@ -242,16 +290,17 @@
        end
      endcase // case(phase)
    
+
    always @*
      case(phase)
-       4'd1 : fifodata_16 = ch_0_reg;
-       4'd2 : fifodata_16 = ch_1_reg;
-       4'd3 : fifodata_16 = ch_2_reg;
-       4'd4 : fifodata_16 = ch_3_reg;
-       4'd5 : fifodata_16 = ch_4_reg;
-       4'd6 : fifodata_16 = ch_5_reg;
-       4'd7 : fifodata_16 = ch_6_reg;
-       4'd8 : fifodata_16 = ch_7_reg;
+       4'd1 : fifodata_16 = ch_0_buff0;
+       4'd2 : fifodata_16 = ch_1_buff0;
+       4'd3 : fifodata_16 = ch_2_buff0;
+       4'd4 : fifodata_16 = ch_3_buff0;
+       4'd5 : fifodata_16 = ch_4_buff0;
+       4'd6 : fifodata_16 = ch_5_buff0;
+       4'd7 : fifodata_16 = ch_6_buff0;
+       4'd8 : fifodata_16 = ch_7_buff0;
        default : fifodata_16 = 16'hFFFF;
      endcase // case(phase)