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[Commit-gnuradio] git://gnuradio.org/jcorgan-uhd branch, gpio, updated.
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[Commit-gnuradio] git://gnuradio.org/jcorgan-uhd branch, gpio, updated. fa99439442530035d222ad1fd956acb2464736c7 |
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Thu, 8 Mar 2012 03:27:15 +0000 (UTC) |
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- Log -----------------------------------------------------------------
commit fa99439442530035d222ad1fd956acb2464736c7
Author: Johnathan Corgan <address@hidden>
Date: Wed Mar 7 16:32:13 2012 -0800
gpio: rework GPIO FPGA implementation to use new async payload
* All constraints met w/N2x0, USRP2 not tested
commit 5b0277781467255ab3768220f93ed8add8d80760
Merge: 5f3d024 b61f4ad
Author: Johnathan Corgan <address@hidden>
Date: Tue Mar 6 12:50:31 2012 -0800
Merge remote branch 'ettus/master' into gpio-merge
* Switch to using custom event code and async metadata payload from
new UHD 3.4.0
* Host code diff on this branch is now only the definition of
USRP2_RX_GPIO_SID and adding it to the if clause in the receive
pirate loop.
Conflicts:
host/include/uhd/types/metadata.hpp
host/lib/usrp/usrp2/io_impl.cpp
commit b61f4ad603b43e8c257bf4bcca924368d5573c92
Author: Josh Blum <address@hidden>
Date: Wed Feb 29 14:26:40 2012 -0800
usrp1: fix for cordic init, cant do it that way on tx
commit 757dd0915ee4a32c65c940d7bc255ae812fa6b6a
Author: Nicholas Corgan <address@hidden>
Date: Wed Feb 29 09:28:53 2012 -0800
Changes Windows installer filename to match naming convention of Ubuntu and
Fedora installers
commit a58ee6e29a9859b7eebb261fdcddf60de627c1aa
Author: Josh Blum <address@hidden>
Date: Wed Feb 29 09:52:46 2012 -0800
uhd: fix sc16 to sc8 conversion table
1) this was registered as the sc8 to sc16 converter,
probably messed that up as well
2) the cast to index was wrong, now unit test passes
commit fedad06362e22f8a171bfe8ae0b747492d22de1d
Author: Josh Blum <address@hidden>
Date: Wed Feb 29 09:30:03 2012 -0800
usrp2: device locking tweaks
1) use bottom bit for force lock condition,
that way we never check the time after proper shutdown
2) dont allow lock condition under fpga compat mismatch
commit 84567c2033fcd6aa5e297ab76ea3684baef0c665
Author: Ben Hilburn <address@hidden>
Date: Tue Feb 28 15:54:51 2012 -0800
Changing UHD to 'USRP HD' in one last place.
commit bd7e53d385431d792a8f7b3a006c3ba5c5d0867d
Author: Josh Blum <address@hidden>
Date: Tue Feb 28 13:35:50 2012 -0800
usrp: reset cordics on init after tick rate update
commit aa422ece8206ad40dcc27aa31fcaeb6edd8f3e20
Author: Nicholas Corgan <address@hidden>
Date: Tue Feb 28 13:24:46 2012 -0800
Changes images CMakeLists.txt to be consistent with new UHD version naming
system
commit dfaf1f930ce0ff7219c0d10fc0156cba0e46950a
Author: Josh Blum <address@hidden>
Date: Mon Feb 27 15:45:59 2012 -0800
uhd: fixed some compile warnings for msvc
commit 2033713db5ca6224bc769747420458287eecc506
Author: Nicholas Corgan <address@hidden>
Date: Tue Feb 28 09:17:26 2012 -0800
cmake:
More git info used for build info
UHD version incorporates build info
apt/yum repos use new version number
New installer filename syntax
commit f591c4a80853a8ede173d36fad0049f19ae79636
Author: Josh Blum <address@hidden>
Date: Mon Feb 27 15:40:06 2012 -0800
uhd: fixed send pkt handler, vrt packet type was uninitialized
This fixes a bug where the sc8 engine will not interpret
the packet as an IF data packet due to uninitialized bits.
In that case the sc8 packet would pass through and be
interpreted by the downstream as an sc16 packet.
commit 12260e71f4df4f872a1f5086fd50b8f7ac1408d2
Author: Josh Blum <address@hidden>
Date: Mon Feb 27 11:37:23 2012 -0800
usrp2: removed unused memory map entries
commit 11e9429b9515f4e6315b867dbe2fcd17bd8a96a8
Author: Josh Blum <address@hidden>
Date: Fri Feb 24 10:00:44 2012 -0800
usrp1: fix to use the db connection type to determine DAC sign
Unlike the other products, usrp1 uses the DAC and not DSP
to perform baseband frequency shifting in the hardware.
Therefore this shifting occurs before I and Q swapping,
and so, the sign of the frequency needs to be inverted
on daughterboards which have inverted I and Q TX inputs.
commit 1156d9b26a59ae45ec34b2fcb7ac782f4bf03b40
Author: Josh Blum <address@hidden>
Date: Tue Feb 21 17:42:15 2012 -0800
usrp1: fix advertised samples per packet in send streamer
Must subtract off the 511 for 512 modulus remainder commit.
This bug was introduced by the conversion to streamer API.
commit 1c29b595accd6c270d3d7864caf9cccea88e9c4e
Author: Philip Balister <address@hidden>
Date: Tue Feb 21 14:34:02 2012 -0500
Try really hard to get cmake to use compiler flags from the toolchain file.
See: http://www.mail-archive.com/address@hidden/msg33248.html
Also credit to OpenEmbedded for doing something similar in the toolchain
file
they create.
Note that adding the SYSTEM_NAME to the toolchain file sets CROSS_COMPILING,
which is not what we want for native compiling.
Signed-off-by: Philip Balister <address@hidden>
commit f0ac072a82fdd90438c2826e02aed0546be96014
Author: Josh Blum <address@hidden>
Date: Tue Feb 21 08:46:31 2012 -0800
usb: added /opt/local to libusb search path
For OSX from MLD
commit 2e85c4a2f1f36d5afb95c13c1f6033cf873ac6f0
Author: Josh Blum <address@hidden>
Date: Mon Feb 20 15:33:42 2012 -0800
usrp2: some tweaks to the device locking logic
commit b1f34b4fd06bd54bcf52860e6d1fe63ad30f2105
Author: Josh Blum <address@hidden>
Date: Sun Feb 12 16:40:07 2012 -0800
usrp2: added retry logic to control packets
commit 0df49b75024dbf205effa5bd8530173423a4d7a8
Author: Josh Blum <address@hidden>
Date: Sat Feb 18 23:38:11 2012 -0800
usrp2: changed download url for dd.exe
commit f500b92ef52312832e81574f477dbd0308242a25
Merge: e9e670d e230fef
Author: Josh Blum <address@hidden>
Date: Sat Feb 18 22:21:28 2012 -0800
Merge branch 'fpga_master'
commit e230fefb32ad5ec2a861fdfef876da068a702b6a
Author: Josh Blum <address@hidden>
Date: Sat Feb 18 22:15:10 2012 -0800
usrp2/nseries: added churn to meet timing
Added churn to readback mux on nseries to make n200r4 meet timing.
Also added churn to usrp2 for parallelism, but assigned to zero.
commit 026f57d204efc03a421602eb40b572dd9c2d0d2f
Author: Josh Blum <address@hidden>
Date: Sat Feb 18 16:46:56 2012 -0800
vita rx: trigger clear after packet tranfer
To avoid blocking conditions down the pipe,
avoid clearing vita rx during packet transfer.
Adds state machine to delay the clear until after xfer completes.
commit e9e670d7c9ecc6c809795b4a52d57fe612173ca9
Author: Josh Blum <address@hidden>
Date: Sat Feb 18 14:40:21 2012 -0800
uhd: added -fvisibility-inlines-hidden
commit 3ddbcb6078593c39cb0e4bc8f9769f818a61466f
Merge: 1fab7e9 ace4489
Author: Josh Blum <address@hidden>
Date: Fri Feb 17 18:18:26 2012 -0800
Merge branch 'next'
commit ace4489066d1621a09e70650a00d736f0b03ed8c
Merge: 8f8ac33 2e37dd8
Author: Josh Blum <address@hidden>
Date: Fri Feb 17 16:55:59 2012 -0800
Merge branch 'fpga_next' into next
commit 8f8ac3397aaa85b64aaa8722efdc1c0c40e93052
Author: Josh Blum <address@hidden>
Date: Fri Feb 17 16:55:23 2012 -0800
dsp rework: fix for vita occ trailer packing
commit 2e37dd87234e5beddd6f76fcda714916f761f812
Author: Josh Blum <address@hidden>
Date: Fri Feb 17 16:52:41 2012 -0800
dsp rework: fix dspengine_8to16 to handle padded packets
commit 2ad9e0ad6520adda571de8b1afe9d975cc09d311
Author: Matt Ettus <address@hidden>
Date: Thu Feb 16 19:08:31 2012 -0800
dsp_engine: fix for upper/lower swap, and odd length packets
commit 59d06f718130c19f808d898f438a1fcb9cdefc04
Author: Josh Blum <address@hidden>
Date: Wed Feb 15 15:44:44 2012 -0800
dsp rework: added flusher to vita tx chain on clear
commit 831213bd57f0ac41e88f4b741f22885fb8316399
Author: Josh Blum <address@hidden>
Date: Wed Feb 15 15:44:24 2012 -0800
dsp rework: added flusher to vita tx chain on clear
commit 3060006b35859c8766e00d3b234b51a19aa8595f
Author: Josh Blum <address@hidden>
Date: Tue Feb 14 18:26:03 2012 -0800
uhd: added async md user payload and common utils
commit 82d38412e2688bb41967b301ce0de084e82cdeef
Author: Josh Blum <address@hidden>
Date: Tue Feb 14 16:34:36 2012 -0800
b100: use frame boundary to calculate frame size
commit 1463a78fd2ebac1985182dede9c3ec1af11a3799
Author: Josh Blum <address@hidden>
Date: Tue Feb 14 15:01:15 2012 -0800
b100: reset/reenumerate fx2 for bad endpoint state
Determine state of control endpoint,
re-enumerate to put in a known state,
rerun some initialization code.
commit 8bd255c5f6ed586603727ffaa56d1eeb325458af
Author: Josh Blum <address@hidden>
Date: Tue Feb 14 12:03:52 2012 -0800
b100: added transport flushes and moved around reset code
commit 2f21932ae1e8f7cc584eff791dcd67a8ea2ca144
Author: Josh Blum <address@hidden>
Date: Tue Feb 14 11:37:12 2012 -0800
dsp rework: minor fix sph, set has time spec for tsf only
commit df946523010929944cab487669defec2059951d4
Author: Josh Blum <address@hidden>
Date: Mon Feb 13 19:22:26 2012 -0800
uhd: inline time spec accessors for minor improvement
commit 42e906a3345c772f71b57126f754f87c0112d740
Author: Josh Blum <address@hidden>
Date: Mon Feb 13 10:21:46 2012 -0800
dsp rework: minor simplification in vita_tx_deframer
all n-series devices meet timing
commit 1fab7e9d477aa98e489400c25a08358952c69c90
Author: Josh Blum <address@hidden>
Date: Sun Feb 12 14:51:03 2012 -0800
usrp1: big endian compile fix, conversion should cast to unsigned
The htonx only takes unsigned integers, cast the int16 to uint16.
commit 4a27f6e4bdad5e4de743e77f0a998dbe1e852cf0
Author: Josh Blum <address@hidden>
Date: Sun Feb 12 14:38:35 2012 -0800
uhd: add over-the-wire option to tx waveforms
commit bada7617a2941712b68421b647c03623ef21c928
Author: Josh Blum <address@hidden>
Date: Sun Feb 12 14:17:45 2012 -0800
dsp rework: full-rate pipelining in vita tx deframer
The vita tx deframer can now pass payload at clock rate.
This enables TX streaming at interpolations factors of 2.
The vector capabilities of TX deframer have been kept in-tact,
and should be functional, however, only MAXCHAN=1 has been tested.
commit 6d45600ada785cb50a01a17dcddf561d12501d22
Author: Josh Blum <address@hidden>
Date: Fri Feb 10 12:13:51 2012 -0800
dsp rework: pass enables into glue, update power trig, parameterize, fix
module inc
DSP enables now pass through the glue and custom modules so it can be
user-controlled.
Updated power trigger to current spec, and added comments
Pass width from dsp into glue, and use width to parameterize wires
Fix custom module includes so they will build
commit 8442ea5e2cfec89db6e58736a969da2842734631
Author: Josh Blum <address@hidden>
Date: Thu Feb 9 19:02:43 2012 -0800
b100/usrp1: various tweaks for compiler warns and valgrind
commit 115100034071b3b58de1fce7c795995f6ee615a1
Author: Josh Blum <address@hidden>
Date: Thu Feb 9 17:59:48 2012 -0800
uhd: various tweaks for compiler warns and valgrind
commit b6da2fe9af84663fa4dda923833e2319433b6f20
Author: Josh Blum <address@hidden>
Date: Thu Feb 9 17:06:37 2012 -0800
uhd: fixed sse2 conversion fc32 to sc8_item32_be
commit 4044a9eeb6fb195b8e64cd1879b0d40973dc27cb
Author: Josh Blum <address@hidden>
Date: Thu Feb 9 16:54:08 2012 -0800
uhd: fixed orc conversion fc32 to sc8_item32_be
commit 10a4d951a1548a99cfd7ac8c015e0bb18ce5e343
Author: Nick Foster <address@hidden>
Date: Thu Feb 9 10:53:39 2012 -0800
B100: Firmware reset tweaks.
commit cfba2388ce71121bbadbf0366dbf95f726e78748
Author: Josh Blum <address@hidden>
Date: Wed Feb 8 23:01:46 2012 -0800
uhd: added sse2 conversions for fc32 to sc8
commit d46684710950a6695ee22c079327253a91eb268d
Author: Josh Blum <address@hidden>
Date: Wed Feb 8 19:22:38 2012 -0800
uhd: added sse2 conversions for fc64 to sc8
commit 122b9477c5e3a3f63789aeb1d3d8ae572ef2cec7
Author: Josh Blum <address@hidden>
Date: Wed Feb 8 14:24:17 2012 -0800
windows: do not set process wide priority from thread prio
commit 52a10572378d627d3b9467d02fa2b3244bd3cb44
Author: Nick Foster <address@hidden>
Date: Wed Feb 8 13:44:52 2012 -0800
Add Orc functions to convert to sc8. bswap version is a bit of a hack.
commit 9429905c9713bef42cd7358d01c173eafda0d29e
Author: Josh Blum <address@hidden>
Date: Wed Feb 8 13:12:44 2012 -0800
e100: loopback test fix after register tweaks
commit 2a79f1928087660b07e183dd81e259fa764a9945
Author: Josh Blum <address@hidden>
Date: Wed Feb 8 12:37:58 2012 -0800
uhd: better quantization check for convert test
commit ec58790efbcbea2732303b1980537aec1438ee03
Author: Ben Hilburn <address@hidden>
Date: Tue Feb 7 17:33:53 2012 -0800
Fixing TX mixer disable, maxing out attenuation when not in use.
commit 9cc4c37fb48eb188834908448706920b193b8766
Author: Ben Hilburn <address@hidden>
Date: Tue Feb 7 17:27:23 2012 -0800
Fixing ADF4351 dividers, even though they won't get used.
commit 1bef34879ef3dcbfc411f711f0ab2aacaf10368c
Author: Ben Hilburn <address@hidden>
Date: Tue Feb 7 17:27:05 2012 -0800
Random formatting while reading through ATR.
commit 893af3dc280a5d85be2a5beb266dba9bb538292c
Author: Josh Blum <address@hidden>
Date: Tue Feb 7 11:59:42 2012 -0800
uhd: added sc8 conversion tests
commit 5eec31fab45649b529428cda756d04bcdaeb3134
Author: Josh Blum <address@hidden>
Date: Mon Feb 6 16:40:42 2012 -0800
dsp rework: implement 64 bit ticks, no seconds
commit 34db74740704ce2de2a71447b3d202e9c4be800b
Author: Josh Blum <address@hidden>
Date: Mon Feb 6 16:40:17 2012 -0800
dsp rework: implement 64 bit ticks no seconds
commit 947d0ffabc72b1f74ff4507df12b6bf2a021dc3b
Author: Nick Foster <address@hidden>
Date: Mon Feb 6 13:01:32 2012 -0800
B100: External FPGA reset from FX2 reuses fpga_cfg_cclk.
commit 5c56ca574ffdf7ad469ab3a3f54def944a978bee
Author: Nick Foster <address@hidden>
Date: Mon Feb 6 13:01:15 2012 -0800
B100: use FPGA external reset on init
commit 5f3d0248d5a37c4a3b16a22bfe6b97bc6f5c0301
Merge: 23669eb 5b06adb
Author: Johnathan Corgan <address@hidden>
Date: Sun Feb 5 09:10:29 2012 -0800
Merge remote branch 'ettus/master' into gpio
commit a9d307124faa679df8180b5624e9250555306d67
Author: Josh Blum <address@hidden>
Date: Sat Feb 4 16:38:54 2012 -0800
dsp rework: pass vita clears into dsp modules, unified fifo clears
commit c6e63c9d2af2c0b2e168aa6fdd63fe7b214927de
Author: Josh Blum <address@hidden>
Date: Sat Feb 4 16:38:15 2012 -0800
b100/e100: unify rx/tx fifo clears into one
commit 1e3cb86432ee1d695a12fd99590206e43caab2cc
Author: Josh Blum <address@hidden>
Date: Sat Feb 4 15:12:37 2012 -0800
uhd: added/renamed various readme files
commit 89ce89c9aca6daf7e293b80c70e14a3e2710e137
Author: Josh Blum <address@hidden>
Date: Sat Feb 4 15:12:03 2012 -0800
b100: timing constraints on GPIF lines
commit 04e9d23d5f9f300164182597b0e0525063bd91e4
Author: Josh Blum <address@hidden>
Date: Sat Feb 4 08:41:54 2012 -0800
b100: delete some unused registers from map
commit 0d2acffaf4d3e3b02dc9745e94b407356650f923
Author: Nick Foster <address@hidden>
Date: Fri Feb 3 17:36:07 2012 -0800
B100/B150: firmware disable FIFOs until host enables to keep junk out
commit 1b489be22ca07a949a9bea59f0040c0c3d770d8a
Author: Josh Blum <address@hidden>
Date: Fri Feb 3 15:35:07 2012 -0800
b100: connect all clears for gpif
commit f88dd2289b714b53a59d0fd6da1ddef549940e51
Author: Josh Blum <address@hidden>
Date: Fri Feb 3 10:57:49 2012 -0800
dsp rework: added otw mode for benchmark app
commit ae1997f869695726c71cb671bb80e29709c9888d
Author: Matt Ettus <address@hidden>
Date: Thu Feb 2 20:57:39 2012 -0800
power_trig: test code for power trigger
commit 97a8f455c1c023d39e72138a736f08c97dbfe346
Author: Josh Blum <address@hidden>
Date: Thu Feb 2 20:09:28 2012 -0800
dsp rework: move setting address of format register
commit e64b6e6cddc2f9a5374cf23dbb8cf066d2fecbf8
Author: Josh Blum <address@hidden>
Date: Thu Feb 2 20:08:47 2012 -0800
dsp rework: rehash of the custom module stuff and readme
commit 1ce83a07e188844d81db62d9e3027267fae97fb7
Author: Matt Ettus <address@hidden>
Date: Thu Feb 2 17:57:53 2012 -0800
power_trig: first cut at power trigger with fixed delay
commit b7ff81c9a8316bb0310d9291afe722c48b441f29
Author: Josh Blum <address@hidden>
Date: Thu Feb 2 15:15:54 2012 -0800
dsp rework: work on usb wrapper for smaller packets, large luts
commit 17f5776c9cac89516a82b1e8f84f8a2dcc1a16ad
Author: Matt Ettus <address@hidden>
Date: Thu Feb 2 11:00:52 2012 -0800
dsp_rework: testbench enhancements
commit 95f8d2a35606e9e42f61bed48ade1217dea1eed3
Author: Josh Blum <address@hidden>
Date: Thu Feb 2 01:34:40 2012 -0800
uhd: updated sync docs for current API
commit 5e972e7446edb79f8ed582970b2dff40a93919ae
Author: Josh Blum <address@hidden>
Date: Wed Feb 1 18:02:59 2012 -0800
b100: sc8 mode not implemented error
commit 7e6a08556b01fcb6ad113c2ff0db4abe5aeac38f
Author: Josh Blum <address@hidden>
Date: Wed Feb 1 18:02:10 2012 -0800
dsp rework: custom engine module for rx/tx vita chain
commit 6bbcb202183c5a0ab5351a0c052981408e4719cb
Author: Josh Blum <address@hidden>
Date: Wed Feb 1 16:35:08 2012 -0800
dsp rework: register the sample in vita tx ctrl
commit 6525ddaf39e96707eff14b2131dc210494415a68
Merge: c407516 111216e
Author: Josh Blum <address@hidden>
Date: Wed Feb 1 13:41:07 2012 -0800
Merge branch 'slave_fifo_rebase' into dsp_rework
Conflicts:
usrp2/top/B100/u1plus_core.v
commit a0887f3bd37e840f5b8ccb894478213e5eae7ed1
Author: Josh Blum <address@hidden>
Date: Thu Jan 12 20:05:38 2012 -0800
b100: bump compat numbers for slave fifo mode
Conflicts:
host/lib/usrp/b100/b100_impl.hpp
commit be14ffa819f2c88d24903d01a32eb85afc182a7d
Author: Nick Foster <address@hidden>
Date: Thu Jan 12 11:43:40 2012 -0800
B100: Modified TX send size to achieve 10.7Msps.
commit 081714b4ce40701067e5513127dd9b9322cbfa5d
Author: Nick Foster <address@hidden>
Date: Thu Jan 12 11:03:43 2012 -0800
B100 firmware changes to allow slave mode TX/RX.
commit 81b4689cf5a16b71c85b4a0f94746d61091fa29f
Author: Nick Foster <address@hidden>
Date: Thu Jan 12 10:58:42 2012 -0800
B100 host code changes to remove TX padding, remove RX padding, increase
max allowed rate.
commit d27125b9ab86e0d44db1317707aff7e9f9f8f32f
Author: Josh Blum <address@hidden>
Date: Wed Feb 1 09:48:28 2012 -0800
dsp rework: account for no sid used in tx vita pkt
commit c407516349601831767952a9b12a077a2f23ea51
Author: Josh Blum <address@hidden>
Date: Wed Feb 1 09:47:07 2012 -0800
dsp rework: paramaterize post_engine_buffering
commit 7b69532aca8cc44017dedc1bfb07fa0d27b8ea6d
Author: Matt Ettus <address@hidden>
Date: Tue Jan 31 17:22:12 2012 -0800
dsp_rework: handle longer headers
commit d46c176af34b728fd43b3dd46485b38623a7335e
Author: Josh Blum <address@hidden>
Date: Mon Jan 30 22:23:38 2012 -0800
dsp rework: tx trailer, scaling work (peak)
commit 781cafa8717f00b883a4543b4a9150060691eee3
Author: Josh Blum <address@hidden>
Date: Sat Jan 28 17:21:40 2012 -0800
gen2: added user setting regs api and user core
commit aa95e53a91fa52b61b6796fcfc811251b20dcb73
Author: Josh Blum <address@hidden>
Date: Sat Jan 28 16:08:17 2012 -0800
dsp rework: work on scaling and args parsing on RX and TX dsp
This simplified some copy pasta in the io_impl.cpp files,
and adds a place for sc8 tx mode in the tx dsp core code.
commit 8f25550d1a8ac634ee3873ae90a86d1e07dd5482
Author: Josh Blum <address@hidden>
Date: Sat Jan 28 12:21:01 2012 -0800
dsp rework: implemented new scalefactor in rx dsp core
commit 72359ea15846ab87c781ab4d072f694e97cc3cd1
Author: Josh Blum <address@hidden>
Date: Tue Jan 17 13:42:37 2012 -0800
uhd: implement convert_sc8to_sc16 table w/ scalar
commit 5b06adb7911727353938df84a0a6b71cda66c95c
Author: Josh Blum <address@hidden>
Date: Tue Jan 31 14:44:35 2012 -0800
uhd: branch-less round for time spec convert to ticks
This fixes valgrind warnings with branching on unit'd values,
and possible exceptions thrown on bad unit'd values.
As it turns out, sometimes tick_rate was passed unit'd,
however, the value calculated was not of consequence.
Also, iround was overkill because we dont need to handle
negative tick rates or frac seconds, or bounds checking.
commit 08b60ada2f025deac298faa2492c838db7c31d10
Author: Matt Ettus <address@hidden>
Date: Tue Jan 31 12:06:22 2012 -0800
dsp_rework: more thorough test
commit 531a7910c22dce40de5ddccee0cb05275b73fe32
Author: Josh Blum <address@hidden>
Date: Mon Jan 30 23:04:31 2012 -0800
dsp rework: finished engine HEADER_OFFSET stuff, add post_engine_buffering
commit 327c25864e3d09fdc34fe9f438dded1329b0c65c
Author: Josh Blum <address@hidden>
Date: Mon Jan 30 22:22:56 2012 -0800
dsp rework: work on 8 to 16 engine (usrp2 ok)
commit 9803334f95c548b7fdf9a9d73c41e6e22f252dcb
Author: Matt Ettus <address@hidden>
Date: Mon Jan 30 16:35:07 2012 -0800
dsp_engine: work with transport header
commit 05644d7d4fe2df455b01833cc0fc8aa1b4b6e1f3
Author: Josh Blum <address@hidden>
Date: Mon Jan 30 15:09:47 2012 -0800
dsp rework: integrated dspengine_8to16, some tweaks
commit ac35b413a595617c1fa57766758c06ccfe3f320e
Author: Matt Ettus <address@hidden>
Date: Sun Jan 29 18:23:23 2012 -0800
dsp: 8 to 16 bit conversion for tx side. believed to be functional
commit 724e4a9eba417bb053259f312060e5e3ebe4581d
Author: Josh Blum <address@hidden>
Date: Sat Jan 28 16:01:30 2012 -0800
dsp rework: increase the number of effective bits in the duc scale factor
This will be useful for effecting the dynamic range of the sc8 tx mode.
commit 15a717c0ad95bb93b6740a187afbc781a860a39d
Author: Josh Blum <address@hidden>
Date: Sat Jan 28 14:26:53 2012 -0800
dsp rework: added double buffer interface to vita tx
commit 9f9729993197839d8be950d69eca4456c8e41323
Author: Josh Blum <address@hidden>
Date: Sat Jan 28 12:21:15 2012 -0800
dsp rework: moved scale and round into ddc chain
16to8 engine now performs only a clip from 16->8
commit 0ff51a352d13f2ce6c59c82c90e853720936c88f
Author: Josh Blum <address@hidden>
Date: Fri Jan 27 21:19:47 2012 -0800
dsp rework: top level fixes B100/E100
commit 4f94819a4422a71251661fb501412565ffaea8be
Author: Josh Blum <address@hidden>
Date: Fri Jan 27 19:20:54 2012 -0800
dsp rework: integrated custom dsp module shells
commit e30cf4ec6d3c5e5c83fdb8e4ee39632fdb46c0df
Author: Josh Blum <address@hidden>
Date: Fri Jan 27 19:09:58 2012 -0800
usrp1/b100: reenumeration loop with timeout only when found
commit bcda4624deb5a81ba2ad338157c44855dab56397
Author: Josh Blum <address@hidden>
Date: Fri Jan 27 13:20:34 2012 -0800
dsp rework: implemented dsp changes for other top levels
added user registers into each toplevel (not used yet)
commit 837437c65ce36d418cceb3df5b093f9497b3af5f
Author: Jason Abele <address@hidden>
Date: Wed Jan 25 13:00:07 2012 -0800
Swap I/Q on transmit
commit e633f884d728c24e6f5749d5821b9c62ec8fd17e
Author: Josh Blum <address@hidden>
Date: Fri Jan 27 11:52:19 2012 -0800
dsp rework: renamed dsp signals for frontend IO
commit cbea8a3b14412b513b54167b745307a102f2fe68
Author: Josh Blum <address@hidden>
Date: Thu Jan 26 19:00:07 2012 -0800
dsp rework: u2_core test implementation
commit c09e881718a083609050201d197516d1ed9a74a4
Author: Josh Blum <address@hidden>
Date: Tue Jan 17 15:32:23 2012 -0800
usrp1/b100: handle longer reenumerations with loop and timeout
commit 9f2aa9235f01b531966a8903583a2044fec1455d
Author: Josh Blum <address@hidden>
Date: Mon Jan 16 23:04:53 2012 -0800
uhd: add samples per pkt option to rx streamer
commit cbeb4305b59d4b9370bfa7c6f5da7597f9de8045
Author: Josh Blum <address@hidden>
Date: Tue Jan 24 08:38:36 2012 -0800
usrp2: same change but to fw updater
commit d2e4354f7842d7adbdb11367cd8e98af6e463c14
Author: Josh Blum <address@hidden>
Date: Tue Jan 24 08:27:48 2012 -0800
usrp2: firmware should reset dsp on icmp pkt
1) This should kill any streaming,
the previous calls would just stop continuous streaming
2) The breaks were changed to returns
to avoid reprogramming the framer.
commit 111216e5cd579996ec8f498e155e9485580327e6
Author: Nick Foster <address@hidden>
Date: Mon Jan 23 11:09:41 2012 -0800
Fix missing B100 core_compile (poor Git hygeine)
commit b36ab78c18d7c68ad9c9367004ff8decfb2ce817
Author: Josh Blum <address@hidden>
Date: Thu Jan 12 18:54:04 2012 -0800
b100: bumped fpga compat number for slave fifo mode
commit 59b3885e195570f7797b0d73a7162508bbb693ee
Author: Nick Foster <address@hidden>
Date: Thu Jan 12 17:26:49 2012 -0800
Slave FIFO: fix for PKTEND not asserting @ end of RX.
commit a2bb47b824e498cd10a190fac7fb2fdb2da074d0
Author: Nick Foster <address@hidden>
Date: Thu Jan 12 13:45:09 2012 -0800
B100: moar buffering on TX for better performance in bidirectional
applications
commit 3f7ff03c098b5bdbc1134a33c1ea14953f1c2f6f
Author: Nick Foster <address@hidden>
Date: Thu Jan 12 11:14:10 2012 -0800
Squashed slave mode changes onto master.
-----------------------------------------------------------------------
Summary of changes:
README.txt | 19 +
firmware/README | 6 -
firmware/README.txt | 31 ++
firmware/fx2/b100/usrp_common.c | 57 ++-
firmware/fx2/b100/usrp_main.c | 153 +------
firmware/fx2/b100/usrp_regs.h | 28 --
firmware/fx2/common/fx2regs.h | 17 +-
firmware/zpu/apps/txrx_uhd.c | 18 +-
firmware/zpu/lib/memory_map.h | 13 +-
firmware/zpu/usrp2p/udp_fw_update.c | 8 +-
fix-copyright-years | 71 ---
fpga/README | 4 -
fpga/README.txt | 78 ++++
fpga/usrp2/control_lib/Makefile.srcs | 3 +-
fpga/usrp2/control_lib/double_buffer_tb.v | 109 ++++-
fpga/usrp2/control_lib/user_settings.v | 63 +++
fpga/usrp2/custom/custom_dsp_rx.v | 71 +++
fpga/usrp2/custom/custom_dsp_tx.v | 71 +++
fpga/usrp2/custom/custom_engine_rx.v | 53 +++
fpga/usrp2/custom/custom_engine_tx.v | 57 +++
fpga/usrp2/custom/power_trig.v | 130 ++++++
fpga/usrp2/custom/power_trig_tb.v | 71 +++
fpga/usrp2/gpif/Makefile.srcs | 1 +
fpga/usrp2/gpif/packet_reframer.v | 34 +-
fpga/usrp2/gpif/slave_fifo.v | 467 ++++++++++++++++++++
fpga/usrp2/gpio/Makefile.tb | 32 +-
fpga/usrp2/gpio/gpio_context_pkt.v | 52 +--
fpga/usrp2/gpio/gpio_sender.v | 55 +--
fpga/usrp2/gpio/gpio_sender_tb.v | 9 +-
fpga/usrp2/sdr_lib/Makefile.srcs | 9 +-
fpga/usrp2/sdr_lib/cordic_z24.v | 2 -
fpga/usrp2/sdr_lib/ddc_chain.v | 190 ++++++++
fpga/usrp2/sdr_lib/dsp_core_rx.v | 144 ------
fpga/usrp2/sdr_lib/dsp_core_rx_old.v | 200 ---------
fpga/usrp2/sdr_lib/dsp_core_rx_tb.v | 10 +-
fpga/usrp2/sdr_lib/dsp_core_rx_udp.v | 200 ---------
fpga/usrp2/sdr_lib/dsp_rx_glue.v | 98 ++++
fpga/usrp2/sdr_lib/dsp_tx_glue.v | 98 ++++
fpga/usrp2/sdr_lib/dspengine_16to8.v | 38 +-
fpga/usrp2/sdr_lib/dspengine_8to16.v | 203 +++++++++
fpga/usrp2/sdr_lib/{dsp_core_tx.v => duc_chain.v} | 74 ++--
fpga/usrp2/sdr_lib/dummy_rx.v | 2 +-
fpga/usrp2/timing/time_64bit.v | 48 +--
fpga/usrp2/timing/time_compare.v | 44 +--
fpga/usrp2/top/B100/B100.ucf | 16 +-
fpga/usrp2/top/B100/B100.v | 16 +-
fpga/usrp2/top/B100/Makefile.B100 | 16 +-
fpga/usrp2/top/B100/core_compile | 2 +-
fpga/usrp2/top/B100/timing.ucf | 9 +
fpga/usrp2/top/B100/u1plus_core.v | 122 +++--
fpga/usrp2/top/E1x0/Makefile.E100 | 11 +-
fpga/usrp2/top/E1x0/Makefile.E110 | 11 +-
fpga/usrp2/top/E1x0/core_compile | 2 +-
fpga/usrp2/top/E1x0/u1e_core.v | 102 +++--
fpga/usrp2/top/N2x0/Makefile.N200R3 | 12 +-
fpga/usrp2/top/N2x0/Makefile.N200R4 | 11 +-
fpga/usrp2/top/N2x0/Makefile.N210R3 | 12 +-
fpga/usrp2/top/N2x0/Makefile.N210R4 | 11 +-
fpga/usrp2/top/N2x0/u2plus_core.v | 106 +++--
fpga/usrp2/top/USRP2/Makefile | 12 +-
fpga/usrp2/top/USRP2/u2_core.v | 103 +++--
fpga/usrp2/vrt/Makefile.srcs | 2 +
fpga/usrp2/vrt/gen_context_pkt.v | 18 +-
fpga/usrp2/vrt/vita_rx_chain.v | 51 ++-
fpga/usrp2/vrt/vita_rx_engine_glue.v | 95 ++++
fpga/usrp2/vrt/vita_rx_framer.v | 38 +-
fpga/usrp2/vrt/vita_tx_chain.v | 103 +++--
fpga/usrp2/vrt/vita_tx_control.v | 17 +-
fpga/usrp2/vrt/vita_tx_deframer.v | 99 +++--
fpga/usrp2/vrt/vita_tx_engine_glue.v | 99 ++++
host/CMakeLists.txt | 5 +-
host/cmake/Modules/FindUSB1.cmake | 3 +-
host/cmake/Modules/UHDPackage.cmake | 9 +-
host/cmake/Modules/UHDVersion.cmake | 19 +-
host/cmake/Toolchains/arm_cortex_a8_native.cmake | 4 +-
host/docs/sync.rst | 55 +--
host/examples/benchmark_rate.cpp | 15 +-
host/examples/network_relay.cpp | 4 +-
host/examples/test_messages.cpp | 3 +-
host/examples/tx_waveforms.cpp | 5 +-
host/include/uhd/stream.hpp | 13 +-
host/include/uhd/types/metadata.hpp | 21 +-
host/include/uhd/types/time_spec.hpp | 28 ++-
host/include/uhd/usrp/multi_usrp.hpp | 10 +
host/lib/convert/CMakeLists.txt | 4 +-
host/lib/convert/convert_common.hpp | 50 ++-
host/lib/convert/convert_fc32_to_sc8_with_sse2.cpp | 150 +++++++
host/lib/convert/convert_fc32_with_sse2.cpp | 8 +-
host/lib/convert/convert_fc64_to_sc8_with_sse2.cpp | 156 +++++++
host/lib/convert/convert_fc64_with_sse2.cpp | 8 +-
host/lib/convert/convert_orc.orc | 17 +
host/lib/convert/convert_with_orc.cpp | 11 +
host/lib/convert/convert_with_tables.cpp | 100 ++++-
host/lib/convert/gen_convert_general.py | 22 +-
host/lib/transport/gen_vrt_if_packet.py | 2 +-
host/lib/transport/libusb1_zero_copy.cpp | 17 +-
host/lib/transport/super_recv_packet_handler.hpp | 12 +-
host/lib/transport/super_send_packet_handler.hpp | 15 +-
host/lib/transport/usb_zero_copy_wrapper.cpp | 106 +++---
host/lib/types/time_spec.cpp | 59 ++--
host/lib/usrp/b100/b100_ctrl.cpp | 4 +-
host/lib/usrp/b100/b100_impl.cpp | 100 +++--
host/lib/usrp/b100/b100_impl.hpp | 12 +-
host/lib/usrp/b100/b100_regs.hpp | 36 +-
host/lib/usrp/b100/io_impl.cpp | 64 ++--
host/lib/usrp/common/async_packet_handler.hpp | 71 +++
host/lib/usrp/common/fx2_ctrl.cpp | 13 +-
host/lib/usrp/common/fx2_ctrl.hpp | 6 +
host/lib/usrp/cores/CMakeLists.txt | 3 +-
host/lib/usrp/cores/rx_dsp_core_200.cpp | 60 ++-
host/lib/usrp/cores/rx_dsp_core_200.hpp | 3 +-
host/lib/usrp/cores/time64_core_200.cpp | 34 +-
host/lib/usrp/cores/time64_core_200.hpp | 4 +-
host/lib/usrp/cores/tx_dsp_core_200.cpp | 62 +++-
host/lib/usrp/cores/tx_dsp_core_200.hpp | 6 +-
host/lib/usrp/cores/user_settings_core_200.cpp | 43 ++
...spi_core_100.hpp => user_settings_core_200.hpp} | 17 +-
host/lib/usrp/dboard/db_dbsrx2.cpp | 2 +-
host/lib/usrp/dboard/db_sbx_common.cpp | 88 ++---
host/lib/usrp/dboard/db_sbx_common.hpp | 8 +-
host/lib/usrp/dboard/db_sbx_version4.cpp | 4 +-
host/lib/usrp/dboard/db_wbx_version3.cpp | 53 ++-
host/lib/usrp/dboard/db_xcvr2450.cpp | 2 +-
host/lib/usrp/e100/e100_impl.cpp | 25 +-
host/lib/usrp/e100/e100_impl.hpp | 6 +-
host/lib/usrp/e100/e100_regs.hpp | 32 +-
host/lib/usrp/e100/io_impl.cpp | 49 +--
host/lib/usrp/multi_usrp.cpp | 11 +
host/lib/usrp/usrp1/io_impl.cpp | 27 +-
host/lib/usrp/usrp1/soft_time_ctrl.cpp | 4 +-
host/lib/usrp/usrp1/usrp1_impl.cpp | 51 ++-
host/lib/usrp/usrp2/fw_common.h | 4 +-
host/lib/usrp/usrp2/io_impl.cpp | 96 ++---
host/lib/usrp/usrp2/usrp2_iface.cpp | 65 ++-
host/lib/usrp/usrp2/usrp2_impl.cpp | 25 +-
host/lib/usrp/usrp2/usrp2_impl.hpp | 4 +-
host/lib/usrp/usrp2/usrp2_regs.hpp | 12 +-
host/lib/utils/thread_priority.cpp | 4 +
host/lib/version.cpp | 2 +-
host/tests/convert_test.cpp | 83 +++-
host/tests/sph_recv_test.cpp | 24 +-
host/tests/sph_send_test.cpp | 6 +-
host/tests/time_spec_test.cpp | 6 +-
host/usrp_e_utils/usrp-e-loopback.cpp | 3 +-
host/utils/CMakeLists.txt | 2 +-
host/utils/usrp2_card_burner.py | 2 +-
images/CMakeLists.txt | 13 +-
images/{README => README.txt} | 0
148 files changed, 4335 insertions(+), 2084 deletions(-)
create mode 100644 README.txt
delete mode 100644 firmware/README
create mode 100644 firmware/README.txt
delete mode 100755 fix-copyright-years
delete mode 100644 fpga/README
create mode 100644 fpga/README.txt
create mode 100644 fpga/usrp2/control_lib/user_settings.v
create mode 100644 fpga/usrp2/custom/custom_dsp_rx.v
create mode 100644 fpga/usrp2/custom/custom_dsp_tx.v
create mode 100644 fpga/usrp2/custom/custom_engine_rx.v
create mode 100644 fpga/usrp2/custom/custom_engine_tx.v
create mode 100644 fpga/usrp2/custom/power_trig.v
create mode 100644 fpga/usrp2/custom/power_trig_tb.v
create mode 100644 fpga/usrp2/gpif/slave_fifo.v
create mode 100644 fpga/usrp2/sdr_lib/ddc_chain.v
delete mode 100644 fpga/usrp2/sdr_lib/dsp_core_rx.v
delete mode 100644 fpga/usrp2/sdr_lib/dsp_core_rx_old.v
delete mode 100644 fpga/usrp2/sdr_lib/dsp_core_rx_udp.v
create mode 100644 fpga/usrp2/sdr_lib/dsp_rx_glue.v
create mode 100644 fpga/usrp2/sdr_lib/dsp_tx_glue.v
create mode 100644 fpga/usrp2/sdr_lib/dspengine_8to16.v
rename fpga/usrp2/sdr_lib/{dsp_core_tx.v => duc_chain.v} (67%)
create mode 100644 fpga/usrp2/vrt/vita_rx_engine_glue.v
create mode 100644 fpga/usrp2/vrt/vita_tx_engine_glue.v
create mode 100644 host/lib/convert/convert_fc32_to_sc8_with_sse2.cpp
create mode 100644 host/lib/convert/convert_fc64_to_sc8_with_sse2.cpp
mode change 100755 => 100644 host/lib/transport/gen_vrt_if_packet.py
create mode 100644 host/lib/usrp/common/async_packet_handler.hpp
create mode 100644 host/lib/usrp/cores/user_settings_core_200.cpp
copy host/lib/usrp/cores/{spi_core_100.hpp => user_settings_core_200.hpp} (65%)
rename images/{README => README.txt} (100%)
hooks/post-receive
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