[Top][All Lists]
[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Commit-gnuradio] git://gnuradio.org/jcorgan-uhd annotated tag, release_
|
From: |
git version control |
|
Subject: |
[Commit-gnuradio] git://gnuradio.org/jcorgan-uhd annotated tag, release_003_004_000, created. release_003_004_000 |
|
Date: |
Fri, 23 Mar 2012 22:56:21 +0000 (UTC) |
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "git://gnuradio.org/jcorgan-uhd".
The annotated tag, release_003_004_000 has been created
at e8301fe3a86d399d96ae115f68e1c71268cee1c5 (tag)
tagging d97b9deec9141968ef9ed04ddf44bffa860a51c2 (commit)
tagged by Josh Blum
on Wed Mar 21 14:28:50 2012 -0700
- Log -----------------------------------------------------------------
release 3.4.0
Ben Hilburn (16):
Header-include fix: <cstring> for std::memcpy in usrp_e_utils.
Bumping the B100 PID to 0x0002, at Josh's direction.
Changed the udev rules for the new B100 PID.
Renaming 'usrp1_init_eeprom' to 'fx2_init_eeprom', and making it enable
based on
Default adf4350 PLL to fast-lock mode.
Fixing VID comment in firmware to reflect ERLLC rather than FSF.
Adding stuff to the tune request docs.
Small changes / markup on the e1xx documentation.
Simple refactor, lower-cased 'FAT' so users wouldn't think it is an
acronym.
Line-wraps in general docs.
UHD will now print 'L' whenever a late packet is transmitted.
Random formatting while reading through ATR.
Fixing ADF4351 dividers, even though they won't get used.
Fixing TX mixer disable, maxing out attenuation when not in use.
Changing UHD to 'USRP HD' in one last place.
docs: Just added a couple of clarifying notes to the N2Xx docs.
Ian Buckley (37):
Cut debug bus connection to etherenet MAC to make closing timing easier
Checkpoint checkin.
External FIFO tested in simulation and on USRP2 from decimation 64->8
with current head UHD code.
Found bug due to not accounting for the correct number of possible in
flight READ operations that can be in the extfifo pipeline.
Merge branch 'ise12_efifo_work' of address@hidden:ettus/fpgapriv into
ise12_efifo_work
Bringing all coregen files checked in into sync
Adding in files that probably didn;t exist in the ISE10.1 version of
coregen
Edited FIFO instance to delete port that was not regenerated after
reconfiguration
Regenerated FIFO's for extfifo.
Regenerated FIFO with lower trigger level for almost full flag to reflect
logic removed from nobl_fifo.
Added a bunch of debug signals.
Added capacity to the module pinout
Enhanced test bench to be more like real world application
Merge branch 'efifo_merge' of address@hidden:ettus/fpgapriv into
efifo_merge
Added to DCM's and some BUFG's to align the internal 125MHz clock edge
with its presentation externally at the NoBL SRAM.
Enabled phase offset adjustment on DCM_INST1 which drives the external
Fast SRAM clock.
Modified phase shift of DCM1 to -64 which is intended to give more timing
margin on reads from the SRAM at the expense of Writes to the SRAM.
Checkpoint checkin.
External FIFO tested in simulation and on USRP2 from decimation 64->8
with current head UHD code.
Found bug due to not accounting for the correct number of possible in
flight READ operations that can be in the extfifo pipeline.
Bringing all coregen files checked in into sync
Adding in files that probably didn;t exist in the ISE10.1 version of
coregen
Edited FIFO instance to delete port that was not regenerated after
reconfiguration
Regenerated FIFO's for extfifo.
Regenerated FIFO with lower trigger level for almost full flag to reflect
logic removed from nobl_fifo.
Added a bunch of debug signals.
Added capacity to the module pinout
Enhanced test bench to be more like real world application
Added to DCM's and some BUFG's to align the internal 125MHz clock edge
with its presentation externally at the NoBL SRAM.
Enabled phase offset adjustment on DCM_INST1 which drives the external
Fast SRAM clock.
Modified phase shift of DCM1 to -64 which is intended to give more timing
margin on reads from the SRAM at the expense of Writes to the SRAM.
Added external RAM FIFO to u2plus.
Placed 2nd DCM into `ifdef DCM_FOR_RAMCLK which is dissabled by default
Defaulted all SRAM pins to LVCMOS25 8mA FAST
1) u2p has added a new signal from the SRAM to the pinout, RAM_ZZ
1) Created new FIFO IP in Coregen. 512x36 dual clcok FIFO with
programable full watermark
Removed 'ifdef for second DCM that was a deign idea for external SRAM on
u2plus. Hardcoded
Jason Abele (72):
First pass register map complete
Added first wbx dboard code
First pass WBX code, it compiles
Fixed casts in set_freq and attenuator bit mask
Fixed SPI register length
First working RX/TX WBX in UHD
Fixed unguarded debug message
Inverted logic in halfband selection
Refactor WBX and RFX to use conventions more like XCVR
Updated documentation
Fixed USRP2 aux_dac numbering convention
Change WBX frequency range to match actual VCO/divider possibles
Fixes gain range for rfx400 vs other rfx
Fixes gain range for rfx400 vs other rfx
Propogate gain range into RX pga0 helper for RFX boards
Merge branch 'rfx' of ettus.sourcerepo.com:ettus/uhdpriv into rfx
DBSRX support in UHD
Fix DBSRX tuning and filter bandwidth
Created pps_test example and docs
Fixed Assertions to better document tuning failures
Enhance XCVR2450 to clip for high/low band tuning and add bandwidth
property
Added documentation of daughterboard filter bandwidths
Added bandwidth property to all daughterboards
Updated bandwidths in daughterboard docs
Fix Bandwidth for IQ subdevs on Basic/LF
Working DBSRX2 daughterboard code
Working DBSRX2 daughterboard code
Adjusting rx_get and rx_set for newer keys
Added mangling for DBSRX2 i2c addresses on USRP
Updated refclock docs for USRP1, USRP2 and N2XX
Added first pass a swigging dboard iface
Make RFX400 work in UHD
Fix typo in usrp1 external clock modification docs
Hopefully the last typo in external clock mod for usrp1
Fix typo in usrp1 external clock modification docs
Hopefully the last typo in external clock mod for usrp1
Fixes inverted logic in sensors bool interface
Update USRP1 External Clocking docs for set_master_clock()
Correct RFX400 div2 logic, makes RFX400 TX work
Updated documentation and improved XCVR RSSI calculation
Initial SBX-ADI driver
Capture characterization changes
Updating SBX to latest UHD
Makes 2nd SBX proto work
SBX enable LO LPF at 1.5GHz
Handle antenna switching and LEDs
Added RSSI sensor for RFX series (not rfx400)
Added docs for sbx
Make log locking work with picky boost
Added TVRX2 support
Added GPSDO antenna specs
WBX: Add support for WBX v3 daughterboards
Fix rounding in DBSRX2 tuning
Fix rounding in DBSRX2 tuning
Updates to WBX dboard driver for version 3 support
Added notes on latency and through put tuning for UDP
Added documentation for subdevice specifications
Make unknown db complain usefully about antenna selection
Updates to example apps
1 Character Patch for USRP1 usrp_eeprom.bin generation
Fix for unitialized eeprom
Port of daughterboards from wax to new property trees
Updated typos in XCVR2450 dboard property tree code
Clip WBX target freq before computing LO settings
Updates to accommodate loopback calibration mode
rx_samples_to_file is not streaming the correct nsamps
Make TX disable mixer when idle to avoid LO leakage
Make WBX v3+ TX set max attenuation when idle
Swap I/Q on transmit
Fix RSSI measurement
Make DBSRX* set default bandwidth based on codec rate
Disabling the SBX mixer and baseband amp causes grief
Johnathan Corgan (9):
Merged SVN matt/new_eth r10782:11633 into new_eth
Merge branch 'new_eth' of http://gnuradio.org/git/matt into master
Manually assign clk_fpga to BUFG to improve timing
Change bit width of CORDIC constants to remove meaningless warning
Fix missing item on sensitivity list
Remove some warnings in dsp_core_rx
Merge commit 'upstream/master'
Added timing constraint for Wishbone clock/dsp_clock skew
Update config to all eight clock buffers to be used.
Josh Blum (2264):
Merge branch 'udp' of http://gnuradio.org/git/matt into wip/usrp2
Merge branch 'wip/usrp2' of http://gnuradio.org/git/matt into wip/usrp2
skeleton autotools system for uhd
Added stuff for usrp addresses, wax framework, build structure.
Merge branch 'master' of address@hidden:ettus/uhd
removed test file
Created subcomponent for usrp dboards.
Reorganized structure into include, lib, test, firmware, fpga.
added interface for usrp dboards to communicate to mboards
Added base classes for the usrp dboards to inherit.
Added the basic rx and tx skeleton wrapper.
Added strict compiler flags.
Switched dboard ctor arguments with a tuple.
Dboard base class that is no longer also the xcvr.
Integrated cppunit into the build system.
Created device interface for discovery, access, configuration...
Added set time and set time at next pps. Removed the old sync pps
commands, they dont make sense to use anymore.
Added a usrp device abstration that creates usrp mboards.
Added more to the mboard test and the usrp device.
Moved usrp1 fpga files into usrp1 subdir.
Moved usrp2 fpga files into usrp2 subdir.
Merge branch 'usrp1' into usrp2
moved into subdir
Various tweaks, switched to boost unit testing.
Switched from indexed properties to named properties.
Added boost system (needed with asio) and date time (will need for
threading/sleeping).
Added gain handler class to manage wildcard gain settings.
Added dboard id enum.
added utility convenience tune function (wip)
added gpl license v3
Minimal framework in place to handle udp discovery.
Work on the properties framwork with wax::obj.
comments
Made get_link the only way to create nested props.
work on link and proxy args
renamed usrp_uhd to uhd
added transport directory and udp transport
Copied a snapshot of the usrp2 firmware into the microblaze firmware
directory in the uhd repo.
removed dboard files
net_common working in this state with control udp packets
removed unwanted/broken files
Getting hello packets from the usrp2 with ip and mac addrs.
Added a templated dictionary class because its more useful than map.
Made use of templated dict to replace used of map
Reading the dboard ids from the usrp2.
Compiling under old fedora8 with boost 1.37.
Created CMakeLists.txt for a CMake build.
Added CMakeLists.txt for the include dir.
Removed Autotools stuff and the git ignore files.
CMake does not have convenience libraries like automake.
added uninstall target
Added usrp2 impl for the guts of the usrp2 handling.
Created dboard wrapper in the usrp2 impl
Restored microblaze build (accidentally removed makefile ams and
gitignores when doing cmake for host)
Moved the usrp2 implementation files into a usrp2 dir within mboard.
Setting the clock config over control
Added control code in the txrx.c and dboard interface for usrp2 to handle
gpio and atr
moved host code into host directory for clean (unambiguous) top level
Worked out spi api for the dboard interface.
Added i2c control transactions in fw and host
Added control for usrp2 aux dac and adc control.
Flattened the usrp2 impl properties guts.
Added special case for empty dboard slot (none id 0xffff)
added support for the duc (no control yet though)
DUC and DDC control packets OTW
DDC enable with stream at control OTW
Moved lib and include contents of dboard and mboard one directory up and
prefixed them with dboard_ and mboard_.
Made the usrp2 impl into a device.
Made implementation class for the dboard manager.
Moved the udp implementation guts into the cpp file
added set nice gpio pins to manager on init and deconstruct
Work on the io interface for a device (and some implementation work in
usrp2).
Added IF data io handing within the usrp2 impl.
Put fast path code (rx setup) back into txrx.c.
vrt packet count fix
Merge branch 'master' into u1e_uhd
added usrp1e conditional compilation, and checking of device node (aka
file for now)
added usrp1e fpga loader
use a single addr param for the usrp2
Created empty usrp1e cpp file for the case when headers are not found.
made app to load usrp1e fpga images, and tested it to be working
removed empty uhd.hpp and cpp files
fix for io types
Recv noise with uhd.
Send the number of samples per datagram over the control.
The net common is too slow in usrp2 firmware to figure out if its vrt
data.
Expanded the UDP api:
Added a vrt library to pack and unpack from metadata.
Making use of vrt lib in the usrp2 io_impl.
memcpy size fix, change to some send logic
Split metadata into rx and tx specific metadata.
Some tweaks and changes to io impl that fix segfaults.
Moved timeouts into the udp transports.
Added simple device to handle wrapping general properties up into simple
api.
Filled in dboard code for basics and lf type boards.
Cleaned up the gain handler (thing that gets and sets wildcard gains)
Removed freq min and max and gain min, max, and step...
handle getting and setting mac and ip addr from the host
Merge branch 'master' of address@hidden:ettus/uhd into u1e_uhd
Merge branch 'u1e_uhd' of address@hidden:ettus/uhd into u1e_uhd
Device sub classes can register themselves. Simplifies device.cpp
internals.
Ability to burn mac addr and ip addr to usrp2 (over ip/udp for now).
Replaced uses of wax:cast with the templated as method (like in boost
program options).
Added ability to set the subdevices in use for rx and tx dboards.
reimplemented dict to preserve order of insertion
Added recovery app to use raw socket to burn known ip addr.
added more help and verbose on recovery app
changes to get tuning working
got uhd almost compiling in windowze. figured out special flags. also had
to use boost stdint because its missing in visual c++, added a bunch of numeric
casts to reduce warnings
Merge branch 'master' of address@hidden:ettus/uhd into u1e_uhd
define namespace hack when in c compiling
added usrp1e implementation skeleton, began filling it in...
fixed linking and warnings on msvs
created config.hpp to handle export macros, added exports to public api
stuff
compiling under msvc (no idea if it works)
added install path for dll, fixed idiotic msvc error where making a
vector with proxies crashes the app, seems to be ok with the sptr fix, in other
good news, discover usrps works in my vm for the usrp2
Moved typedefs from props.hpp into new file types.hpp.
Added ability to load modules at runtime
Merge branch 'master' of address@hidden:ettus/uhd into u1e_uhd
filled in more skeleton code, filled in dboard interface spi and i2c with
ioctls, added file descriptor opening, and checking for usrp1 kernel header
bit of io work
massaged some of the dboard calls
merged usrp2 stuff from u1e branch (without merging the u1e stuff)
Added example app to receive timed samples.
Reorganized apps dir into utils and examples dir.
added easy way to compile firmware for debug mode
mess with that usrp2 io loop unroll, also py app gets installed executable
Merge branch 'mbdebug' of address@hidden:ettus/uhd into timing
Overhaullllllled the way we do streaming. There is an odd bug where
added interface address discovery
Merge branch 'addrs' of address@hidden:ettus/uhd into timing
insert correct control word and vrt len into the buffer
removed that fw sets seq stuff, not applicable
made python app to generate vrt jump tables, seems to run faster...
library loading on windows, status message tweaks, warning tweaks
get interface addresses on windows
tweak the ifaddrs address discovery
Split utils.hpp into subdir with multiple files.
refactored types.hpp into types directory
minor fix to wax test to get unit testing working on windows, added
missing config include to static.hpp to compile under windows
added some msvc notes, fixed line endings
Added tune helper to utils.
use bb_rate and if_rate to handle dxc io rates
Added utility methods to device addr and mac addr to make them more
usable.
unit test for device addr
Merge branch 'master' of address@hidden:ettus/uhd into usrp_e
compiling with master merge, renamed usrp1e to usrp_e
tweak usrp-e cmake config
Merge branch 'master' of address@hidden:ettus/uhd into usrp_e
filled in some gpio handling code, some mboard impl, added usrp_e_regs
(like memory map)
Added io type and otw type for describing types.
use find to discover devices
removed masks for ddr and gpio write in dboard interface
Refactor ATR part of dboard interface (and some constants).
Moved dsp (rx and tx), time config, and clock config (mostly) into the
host.
added spi slaves to regs, use std copy for buffs
Merge branch 'master' of address@hidden:ettus/uhd into usrp_e
added peek and poke, using in dboard interface
use defined constants for the register addresses
moved props into usrp and multiple hpp files
Moved usrp specific things into usrp directories and namespaces.
hardcoded values for enum props, added clock get/set for simple usrp
windows fix, forgot boost namespace for stdint
env path separator for windows
some work on rfx board code
extended stream cmd with mode enum, and extended fragment flags in
metadata
Added doxygen support.
added 16 bit peek and poke, 16 bit register defs for gpios and atrs
paradigm shift for the dsp abstraction
simplified the usage of dboard, dsp, and mboard proxies.
Merge branch 'rework' of address@hidden:ettus/uhd
some doxygen fixes after merge
renamed dict get key and value methods
handle tx fragment eob flag case
GPIO tested working on usrp.
Merge branch 'master' of address@hidden:ettus/uhd into rfx
added code for adf4360 chip
Reworked the spi part of the dboard interface.
converted timespec to use nanoseconds for fractional part
added python+cheetah build requirement, generating vrt.cpp
generate the register file, added lib include dir
moved regs generator to ic reg maps folder, others will go there as well
put the dummy package back in
Merge branch 'master' into usrp_e
Created zero copy interface/framework, made use of it in usrp2 udp
transport stuff.
Added data type conversion routines to transport api.
store the mtu and hdr len stuff only in the usrp2 impl
Merge branch 'rfx' of address@hidden:ettus/uhd into io
removed dummy placeholder
moved spi transact to usrp2 impl, and removed spi read
Merge branch 'master' of address@hidden:ettus/uhd into usrp2
merged unit type and gpio bank for dboard interface into one type,
expanded dboard clock config api
reg map for ad9510
controlling dboard clock enables from host
forgot dangling file
merge reverse diff
Merge branch 'master' into usrp_e
added reqs and build instructions to readme
Merge branch 'master' of address@hidden:ettus/uhd
Merge branch 'master' of address@hidden:ettus/uhd into usrp2
Moved clock control into abstraction clock control class.
added more clock config, takes care of external reference
added ad9777 register map
Moved ad9777 control 100% on to the host
removed unused firmware code
added adc and dac clock enables
Created a usrp2 interface class with the control, spi, peek/poke
functionality.
work on rfx atr regs
renamed dboard interface to dboard iface, the lengthy name was getting to
be a burden
renamed dxc to dsp for tune result
removed clock rate prop, we dont need to expose that since ticks are in
nsecs
work on atr bits in rfx board
Added gain control to rfx. Switched string constants to caps (gains,
antennas, subdevs).
removed some windows warnings
work on tuning rfx tx and rx LOs
moved usrp1 and usrp2 fpga dirs into fpga subdirectory
Merge branch 'udp'
work on rfx registers
Merge branch 'master' of address@hidden:ettus/uhdpriv into usrp_e
pulled in master and got usrp-e code compiling
RFX seems to be tuning. Added some code to dsp to check for valid range.
forgot an include
added automatic ref source enum
updated readme
moved spi and i2c api into serial.hpp, its used for more than the dboard
interfacing
moved come common register generation code into common.py
Created a docs directory to house restructured text documentation.
added usrp2 networking notes, tweaked style and build
added some documentation and links to the index
Merge branch 'docs' into work
added support for aux dac and adc control in host
pulled aux dac and adc support from microblaze, its in the host now
documentation notes in readme
added comments to cmakelists, makedir in file generation script so python
doesnt have to
Fix script to write board id eeprom.
Fix silly typo in script.
Created args string contructor for device address.
windows warning fix
added coding docs
Merge branch 'win' of address@hidden:ettus/uhdpriv into work
xcvr work, skeleton layout
Added protocol version number to usrp2 common header and data struct.
work on atr registers and filling in functions
added dboard app notes
pulled in some dboard docs and fixes
toggle led a for continuous streaming
added regs for max2829
filled in xcvr tuning, set gain, spi reset
Merge branch 'master' of address@hidden:ettus/uhdpriv into xcvr
xcvr tweaks and fixes, needs real testing
XCVR tweaks, working in highband and lowband.
whoops, copied wrong license
XCVR seems to be working, fixed the spi reset routine.
Merge branch 'xcvr' of address@hidden:ettus/uhdpriv
Moved reading the eeprom (dboard ids) onto the host.
set dboard eeprom from dboard properties
added dboard id burner app
removed boost exception stuff that makes it incompadible with 1.36,
remember this diff
Merge branch 'usrp_e' of address@hidden:ettus/uhdpriv into usrp_e
Work on exceptions.
renamed the firmware main image to txrx_uhd.bin
Added i2c interface to serial.hpp, using in usrp2_iface for i2c and
eeprom.
Got eeprom read/write dboard ids working.
Merge branch 'eeprom' of address@hidden:ettus/uhdpriv
prefixed the ASSERT_THROW macro with UHD for the sake of namespace
added lock detect status to dboards
Renamed the prop set/get error macros so they make sense for
not-implemented properties.
Added RSSI readback to XCVR2450.
added simple usrp api to read rssi and get LO lock status
fixed windows warnings
added to the time spec documentation
Merge branch 'master' of address@hidden:ettus/uhdpriv into usrp_e
usrp-e branch compiling with recent master pulled in
moved i2c into usrp-e interface, used by dboard interface and eeprom
Merge branch 'master' of address@hidden:ettus/uhdpriv
work on controlling the socket buffer sizes from the front end api
setting size of buffers from device args
Added reload flag to the stream cmd.
removed some unused things like gpio from microblaze code
Moved some misc setting registers into host.
Merge branch 'master' of address@hidden:ettus/uhdpriv into usrp_e
Merge branch 'master' of address@hidden:ettus/uhdpriv into usrp_e
work on clock control init, added dummy spi slaves: must fix
use boost program options for env variables
added reg map for ad9862
Moved a bunch of register map code into common.
added ad9522 reg map, minor fixes
Merge branch 'env' of address@hidden:ettus/uhdpriv
Merge branch 'reg_maps'
made buffer size args part of constructor
Merge branch 'socket' of address@hidden:ettus/uhdpriv
added enums to register map
Merge branch 'master' of address@hidden:ettus/uhdpriv into usrp_e
Code tweaks and added unit test for dict and error message.
Merge branch 'usrp_e' of address@hidden:ettus/uhdpriv into usrp_e
Cleaned up some dboard manager construction logic.
Replaced the dboard base constructor args with an opaque type.
Expanded the dboard id API to create dboard id types from strings and
ints.
spi working, talked to ad9522
minor regs fix
Merge branch 'work' of address@hidden:ettus/uhdpriv
minor fix to pass dboard ctor args with correct dbids
windows tweaks to config
added icmp echo reply to usrp2
notes about ping and firewall
Merge branch 'master' of address@hidden:ettus/uhdpriv into usrp_e
created codec control for ad9862, wip
Merge branch 'usrp_e' of address@hidden:ettus/uhdpriv into usrp_e
fix files before pull
Merge branch 'master' of address@hidden:ettus/uhdpriv into usrp_e
Merge branch 'master' of address@hidden:ettus/uhdpriv into usrp_e
Merge branch 'usrp_e' of address@hidden:ettus/uhdpriv into usrp_e
added hb filter calculation on usrp2 dsp impl
Merge branch 'wbx' of address@hidden:ettus/uhdpriv
code tweaks to get wbx compiling with master
Removed the boost exception stuff, replaced it with macro that formats
the throw site information.
fixed exception case
moved uhd lib cmake contents into respective subdirectories
Merge branch 'master' of ettus.sourcerepo.com:ettus/uhdpriv into usrp_e
moved usrp_e specific build stuff into its own cmake file
work on codec control, writing aux dacs, read aux adc
fix for first seqno on rx, init the variable
Merge branch 'master' of ettus.sourcerepo.com:ettus/uhdpriv into usrp_e
Merge branch 'usrp_e' of ettus.sourcerepo.com:ettus/uhdpriv into usrp_e
filled in dboard interface with codec and clock control
moved open/close into iface, work on codec tx
ad9862 transmit working
Merge branch 'udp' of address@hidden:ettus/fpgapriv
added save state for ic regs map common
Merge branch 'shrinkfw' into usrp2
Moved adc and dac control into codec control source file.
Added a place for serdes control on the host.
Moved usrp2 eeprom addr read/write to host control over i2c/eeprom
interface calls.
Added card burner python app with gui and windows support.
notes on usrp2 card burner
work on usrp2 card burner, uses blockdev and /proc/paritions to check for
devices, windows tweaks as well
card burner: added --list option, added warning, added sync on linux
got clock gen config working and tested
fix to ad9777 dac control
memcpy data when in custom io type
card burner notes
added set freq with lo offset to simple usrp wrapper
calculate max samples per packet using otw type
simplification of udp asio socket stuff
windows fix for setsockopt
automatic resize for small udp buffers
work on generic packet handler (got rx working)
Created inline send vrt packer function that also handles fragmentation.
Created config macro to force inline.
use static init lists for the types, some speedup for the fast path
related ones, other changes are pointless
burn sd card fix, units for seek and skip in blocks not bytes
Added send and recv modes to the device class and packet handler
implementation.
Added tx timed samples example.
clock bypass divider fixes, forgot to move this part into the host
Merge branch 'work'
tweaks to remove warning is msvc
Merge branch 'udp' of address@hidden:ettus/fpga into work
init values in dboards to remove gcc warnings
dont default the mode parameter, that is only asking for trouble
break recv loop on timeout
Fixed some bugs in the send and recv full buffer modes.
rfx dboard code minor refactor to look more like xcvr2450 code
Merge branch 'work'
split the card burner into two python apps, one command line app with
implementation, and the other a gui only app, updated docs as well
some wbx series notes
use only procfs /proc/partitions for discovering raw devices on linux
clean up parsing of dd.exe --list for windows usrp2 card burner
mac os x card burner support and documentation notes
fix for time64 register write order
Added timeout error message to timed samples example.
Added support to set GPIO pins from dboard interface:
Tweak with the udp and zero-copy transport. Eventually, the caller will
hang onto a ring of managed buffers.
Merge branch 'master' of ettus.sourcerepo.com:ettus/uhdpriv into usrp_e
reverted usrp-e-led sorry
fix: wrong size for buffer in recv
fix for msvc warning
Made a phony zero-copy interface for those interfaces that are actual
copy-interfaces.
work on buffers for recv
work on bounded and alignment buffer with unit testing
work on alignment buffer, got unit test working
added frame count call to zero-copy iface, tweaks for udp asio impl
Moved the packet handler state stuff into a separate header (so we dont
pull in all the includes).
Merge branch 'buffer' of ettus.sourcerepo.com:ettus/uhdpriv into buffer
Implemented pirate thread, moved io impl details into io impl cpp file.
Fixed bug in bounded buffer push with pop on full.
added sr registers to u1e
use polling for socket recv, timeout socket option not portable
Merge branch 'refactor_db'
use select for socket timeout, works windows and linux
removed some windows warnings
disable boost thread interrupt when doing pop with timed wait, fixed
error on exit
use smart pointer for io impl, simplify send buffer callback
replaced the assert falses with an invalid code path exception
Created macros for dealing with pimpls and implemented in code.
Merge branch 'master' of ettus.sourcerepo.com:ettus/uhdpriv into usrp_e
added headers to cmakelists for completeness
work on io impl for usrp-e using read/write
io impl tweaks, renamed clock control and codec control implementation to
avoid collision with usrp2 (those need to be renamed as well)
recv discovery packets with max size buffer (we dont know what to expect)
Prepend usrp2 onto the helper classes in usrp2 impl to avoid symbol
conflicts.
also use an mtu size recv buffer for the control packet recv
move get clock rate into clock control
prefixed helper classes with usrp_e to avoid collision
Merge branch 'master' of ettus.sourcerepo.com:ettus/uhdpriv into usrp_e
implemented dsp and rx control
usrp-e more implementation, rx timed samples runs w/o error (no workie
though)
usrp2 regs naming convention
moved dsp update logic into prop setter, added code to init dsp rates and
freqs
recv giving me something, bad vrt headers though...
added byteswap routine to utils
Merge branch 'byteswap' into work
Replaced the vrt pack and unpack with a pack and unpack for big endian
and a pack and unpack for little endian.
Merge branch 'work' of ettus.sourcerepo.com:ettus/uhdpriv into usrp_e
Created a common usrp dsp utils to handle register word calculations.
Merge branch 'work' of ettus.sourcerepo.com:ettus/uhdpriv into usrp_e
usrp-e: working vrt recv, implemented dsp utils in usrp-e dsp
Replaced convert types with generated convert types that handles more
cases.
fix to ensure 32 bit swap is called on a 64 bit machine
Merge branch 'wip' into work
float casts to remove msvc warnings
extend byteswap routines for macosx, and added case for unknown
fixed converter logic in convert types
Merge branch 'master' of ettus.sourcerepo.com:ettus/uhdpriv into usrp_e
fix for ad9862 regs map
Merge branch 'master' of ettus.sourcerepo.com:ettus/uhdpriv into usrp_e
usrp-e: switched otw type to little endian (works now)
created capability for meta-registers
created uhd usrp probe
Moved mux calculations into dsp type1 utils.
Merge branch 'probe' of ettus.sourcerepo.com:ettus/uhdpriv into usrp_e
Merge branch 'master' of ettus.sourcerepo.com:ettus/uhdpriv into usrp_e
installed mux setting and initing the duc and ddc
work on algorithms and documentation
file option for rx timed samples, misc fixes
fix type, it was supposed to be complex float
usrp-e: added poll(...) call before read(...) call
usrp2: improved print-out for socket buffer sizing
usrp2: dboard iface: switched to nested dictionary for dac regs
Merge branch 'aux_dac'
Merge branch 'work'
uhd: added ability to boost rt priority, added general app notes
Merge branch 'sched' of ettus.sourcerepo.com:ettus/uhdpriv into usrp_e
usrp2: added a type to the address args to filter based on type usrp2
Merge branch 'sched'
Merge branch 'master' of ettus.sourcerepo.com:ettus/uhdpriv into usrp_e
Merge branch 'master' of ettus.sourcerepo.com:ettus/fpga into uhd_master
usrp-e: added type device address argument to usrp-e
Merge branch 'usrp_e' of ettus.sourcerepo.com:ettus/uhdpriv into usrp_e
uhd: work on thread priority scheduling
uhd: working windows implementation of thread priority setting, added
called to example apps
uhd: check priority range
added set clock rate, and get clock rates to dboard iface, usrp2 needs
clock ctrl implementation...
usrp2: implemented dboard clock divider control in usrp2 clock control
usrp-e: added verbose for bad poll and read values
uhd: added enums for aux adc and dac, usrp2: implemented enums in db iface
usrp2: code and comment tweak for aux dac call
usrp2: enlarged the i2c transaction size, rev-ed the firmware protocol
number, added constants for packet sizes
usrp2 mb: replace hard coded constants with macros for rx offset
Merge branch 'i2c_resize' into pre_merge
Merge branch 'uhd_fpga_merge' into pre_merge
usrp2: updated fpga build notes
uhd: added dboard manager call to register xcvr board, implemented in
xcvr dboard code
uhd: added checking for xcvr dbids, added unknown dboard rx and tx
constructors (for bad dbids or combinations)
Merge branch 'burn_dbid' into pre_merge
usrp2: init clock rate shadows for dboard iface, uhd: pthread sched fix
error condition check
Merge branch 'master' of ettus.sourcerepo.com:ettus/uhdpriv into usrp_e
usrp-e: added clock rate control to dboard iface and clock control impl
usrp-e: clock divider calculation fix
usrp-e: clock control constants to easily change dividers and counters,
tweaks to ic reg maps common
uhd: tweaks to ic regs maps common generator code
Merge branch 'master' of ettus.sourcerepo.com:ettus/fpga into
uhd_fpga_merge
uhd: created benchmark rx example app
uhd: reworked time_spec_t to be more flexible: arithmetic, comparison
operators...
uhd: fix for windows warning, tweaks for msvc optimization flags
uhd: removed hackery to set performance flags, use release mode.
uhd: replaced single sample converters with vector converters
uhd: implemented complex float <-> item32 conversion with sse2
uhd: moved convert routines into implementation header file (out of
python gen file)
uhd: convert types simd, unpack with zero constant for lower half
uhd: moron alert, used incorrect bounds in simd loop, the remainder loop
was doing 3/4 the work
uhd: added build notes for fedora 64 boost not found
Merge branch 'master' of ettus.sourcerepo.com:ettus/fpga into
uhd_fpga_merge
reload bit for vita rx ctrl
usrp2: increased transport buffer minimum size, and added warning
uhd: work vectorizing the vrt packet handler, reworked vrt packet stuff,
needs testing
uhd: forgot burst flags, tweaks to vrt info -> metadata
uhd: vrt packet handler fix and tweaks
usrp2: split mboard impl into its own class, usrp2 device can instantiate
N mboard impls for mimo setup (works with 1 for now)
usrp2: moved calculations for max packet size and otw types into shared
object between device and mboards
uhd: renamed the vrt header to vrt_if_packet header
usrp2: some cleanup and tweaks in io impl
usrp2: removed usrp2.hpp header, its not needed, just use the
discovery/factory system
uhd: filling in mimo usrp implementation, renamed get_name to
get_pp_string for simple and mimo usrp
uhd: filled in mimo usrp rx and tx methods
mimo: added call to set time to zero at next pps on init
uhd: added mimo notes, misc spellcheck and tweaks
uhd: replaced old send and recv with inline wrappers that take a single
buffer and look more like the vectored send/recv
usrp2: bug fix for readback registers
uhd: added get time now call to simple and mimo usrp
uhd: added clear capability to alignment buffer (fixes case when next seq
is less than prev)
uhd: code tweaks, extra error condition for vrt unpack
usrp2: Added a peek64 to read pairs of 32 bit numbers such as time64
uhd: moved header file implementation code into ipp files
uhd: remove windows warnings (minor tweaks)
uhd: added set time w/ unknown pps to mimo usrp, get tx rate bug fix
uhd: added back into old send/recv but with deprecation attributes, moved
inline device stuff into device.ipp
uhd: mimo usrp replace sleep with boost thread sleep (windows fix)
Merge branch 'uhd_fpga_merge'
Merge branch 'usrp2_mimo'
uhd: removed some errors and warnings under macosx gcc build
uhd: renamed prefix on usrp burn eeprom utility
usrp-e: tweaks to clock control logic
usrp-e: removed top level header for usrp-e and fpga burner app, were not
going to do it that way...
Merge branch 'master' of ettus.sourcerepo.com:ettus/uhdpriv into usrp_e
uhd: updated code to build with latest api, not tested
usrp: moved stream cmd word calculation into common dsp utils
Merge branch 'master' of ettus.sourcerepo.com:ettus/uhdpriv into
usrp_e_wip
uhd: added single rate option to benchmark example
Merge branch 'master' of ettus.sourcerepo.com:ettus/uhdpriv into
usrp_e_wip
usrp-e: replaced stream cmd logic with common dsp type1 logic
uhd: added dilv option for timed examples, also made tx timed example
fragment
Merge branch 'master' of ettus.sourcerepo.com:ettus/uhdpriv into
usrp_e_wip
usrp-e: fixed send and recv logic in io impl to deal with frame length
correctly
uhd: change pack/unpack for 64-bit numbers to reflect hardware
implementation
Merge branch 'master' of ettus.sourcerepo.com:ettus/uhdpriv into
usrp_e_wip
usrp2: use the actual pointer in bind so the sptr is not copied
usrp2: moved common defined for udp mtu and implemented change.
usrp2: clean up fw common with nicer looking macro for stdint namespace
uhd: moved assert implementation into ipp file, fixed potential bug with
assert throw macro
usrp2: added notes on multiple device network setup, improved warnings
for buff size stuff
uhd: added packet type to vrt if info struct, added burst flags to rx
metadata, fixed vrt if packet parsing bugs
uhd: callback in vrt packet handler to handle overrun
Merge branch 'error_handling' of ettus.sourcerepo.com:ettus/uhdpriv into
usrp_e
uhd: added error codes to rx metadata, switched examples to use
Merge branch 'error_handling' of ettus.sourcerepo.com:ettus/uhdpriv into
usrp_e
uhd: benchmark app, overruns are ok to get
Merge branch 'error_handling' of ettus.sourcerepo.com:ettus/uhdpriv into
usrp_e
uhd: ssize_t for phony zero copy return types, null sptr for
timeout/error with get managed buffers
Merge branch 'error_handling' of ettus.sourcerepo.com:ettus/uhdpriv into
usrp_e
uhd: define ssize_t for msvc, fixed warning as well
Merge branch 'error_handling' of ettus.sourcerepo.com:ettus/uhdpriv into
usrp_e
usrp-e: added io_impl handle overrun
usrp2: removed SX packet count stuff from vrt packet handler, moved to
usrp2 io impl and replaced with Os
Merge branch 'error_handling' of ettus.sourcerepo.com:ettus/uhdpriv into
usrp_e
uhd: setup metadata for fragment case (not in general case)
Merge branch 'master' of ettus.sourcerepo.com:ettus/uhdpriv into usrp_e
uhd: added checking for time deviation after sync. Prints error.
uhd: support for deb and rpm packages, added dependency requirements
usrp2: forward errors in the dbsm to communicate them up to the host
uhd: switch statements to handle error code, default md to error code none
uhd: add lib64 to boost library path when it exists (helps fedora 64)
uhd: benchmark app, stop if left running initially
uhd: moved cpack stuff into config dir (work on cpack)
uhd: time for version minor, path tweaks, notes on windows command line
compilation
uhd: platform define macros
usrp2: disable buffer resize on platforms that cry about it
uhd: disable cid testing in vrt unit test (not supported)
Merge branch 'master' of ettus.sourcerepo.com:ettus/uhdpriv into usrp_e
uhd: bug in dsp freq word return calculation (signedness)
uhd: fix for vrt packet handler commit size
usrp2: remove mb intervention on outgoing packets
Merge branch 'usrp_e' of ettus.sourcerepo.com:ettus/uhdpriv into usrp_e
Merge branch 'master' of ettus.sourcerepo.com:ettus/uhdpriv into usrp_e
usrp-e: removed vrt header rewrite in io impl, its not in vrt packet
parser stuff
uhd: fix quotes for boost additional versions, restrict lib64 check to
unix platforms
uhd: include code_rate/2 as part of the tunable frequency range
wbx: removed print after freq clip
usrp: added functions to derive tuned frequency, tweaked logic, added
unit test
uhd: added test to check derive_freq_from_xx_subdev_and_dsp
usrp: removed spectrum inverted property from subdev code and tune helper
(it wasnt used)
uhd: work on tune logic, and subdev connection logic
uhd: fix unit test to compile over here
Merge branch 'package'
usrp2: installed a simple dbsm_rx_inspector, it wont work without it...
usrp2: add a timeout to udp control and make it large for usrp2 control
transactions
usrp2: added registers and handling for tx async reports
uhd: typedefed vrt pack/unpack so the vrt packet handler need not be
templated
uhd: bring timeout parameter to the device::recv call, implement in usrp2
Merge branch 'master' into tx_report
uhd: added async recv message call to device api
usrp2: added async event types, and common code for handling context words
uhd: added better throw warning to dict key not found
usrp: changed opaque pointer implementation for dboard contructor args
uhd: get time stamp from git log
usrp2: moved timeout into bound callback in io_impl
uhd: get the version string from the api
usrp: added codec gains props
uhd: moved version extraction code into version.cmake
usrp: fix the N/2 cordic tune issue, use boost math sign inplace of my
signum
uhd: added gain group and unit testing for it
usrp2: added codec impl for codec properties to usrp2
usrp: added gain group support usrp2 dboard and to wrapper implementations
usrp: removed gain handler code (replaced by gain group)
uhd: removed remaining template stuff from vrt packet handler, also
tweaked format in rx timed samples
Merge branch 'tx_report'
usrp2: use default sized buffer on transmit (or reasonably smaller)
uhd: fix find-replace accident asize_t
usrp: added codec gains props
uhd: added gain group and unit testing for it
usrp2: added codec impl for codec properties to usrp2
usrp: added gain group support usrp2 dboard and to wrapper implementations
usrp: removed gain handler code (replaced by gain group)
usrp: gain group should not try to set gain elements if there are none
usrp: codec gains, dont bind function pointers, also add priorities
uhd: alignment buffer timeout abs time fix
uhd: made tx continuous samples example app
usrp2: added tx policy register and changed fw to not handle error in
buffer pool
Merge branch 'tx_policy'
usrp2: stop streaming and drain buffer (if left running)
usrp2: reorganized firmware directory
uhd: docs fix, its 3.3v level
usrp-e: fixed clock div calculation bug
Merge branch 'fw_reorg'
Merge branch 'rfx'
usrp2: added mboard name call to dboard iface
uhd: moved utils cpp files into lib/utils directory
uhd: added warning printer utility function
Merge branch 'master' into codec_gains
dbsrx: modification docs
dbsrx: fix msvc warnings
uhd: use constructor for impl class to avoid msvc warnings
usrp: added subdev spec class with parser to specify subdevice
specifications for channel config
uhd: implemented subdev spec in mimo and simple usrp wrappers.
uhd: created subdevice pair struct for subdev spec (easier than
first/second)
usrp: tweaks to subdev spec printing
dbsrx: added support note to README
uhd: use int to round down for gain group
Merge branch 'codec_gains'
uhd-images: created makefile and cmake packager for the images
uhd: fix device recv docs on timeout, also fix typo
uhd: moved utils specific cmake stuff into utils cmake file
uhd: created library code to handle paths for images and modules
usrp: added api call to get the subdev spec
Merge branch 'features' into uhd_fpga_features
Merge branch 'images'
makefile dependency fix for second expansion
added compat number to usrp2 readback mux
Merge branch 'features' into uhd_fpga_features
Merge branch 'uhd_fpga_features'
usrp2: added fpga compat number, renamed firmware proto version to compat
usrp2: work on card burner to pad the image file before a write
uhd-images: do not require language check for images project
usrp-e: merged master, does not build
usrp-e: fixed warnings and errors, missing subdev spec stuff
usrp: needed default constructor for MSVC, fixed gain group float warnings
Merge branch 'changes'
usrp: added subdev spec verification functions
Merge branch 'subdev_spec' of ettus.sourcerepo.com:ettus/uhdpriv into
usrp_e
usrp-e: filled in properties and logic for subdev spec
usrp-e: removed transfer frameness
Merge branch 'usrp_e_merge' of ettus.sourcerepo.com:ettus/uhdpriv into
usrp_e_merge
uhd: avoid segfaults - use CPP macros for paths and dont split empty
string
uhd: avoid segfaults - use CPP macros for paths and dont split empty
string
uhd: created floor_step to handle floating-point errors in gain group
uhd: made split string utility function
Merge branch 'master' of ettus.sourcerepo.com:ettus/uhdpriv into
usrp_e_merge
Merge branch 'subdev_spec'
usrp-e: fix typo in verify subdev spec
Merge branch 'split_string' of ettus.sourcerepo.com:ettus/uhdpriv into
usrp_e_merge
usrp-e: added codec impl, probe works
usrp-e: codec gain control from properties interface
Merge branch 'split_string' into next
usrp-e: clock settings, ref doubler, disable test clock, lower cp current
usrp1: Cmake changes to find libusb-1.0
usrp: replaced mboard name with special props for dboard iface
usrp: give dboards a name (not a blank string), do automatic selection
when not provided
uhd: extract named prop returns a named prop (not a tuple)
Merge branch 'next' into usrp1
uhd: use cmake to convert the pkg data dir to native system format
Merge branch 'next' into usrp1
usrp1: compiling off next branch
usrp1: created daughterboard duality
usrp1: add skeleton code for setting subdev spec
usrp: moved usrp utils into public include space
usrp: use different priority policies for gain group (rx vs tx)
usrp2: fix missing include
Merge branch 'next' into usrp1_next
usrp1: compiling with the latest next
usrp: needed default constructor for MSVC, fixed gain group float warnings
uhd: avoid segfaults - use CPP macros for paths and dont split empty
string
uhd: created floor_step to handle floating-point errors in gain group
usrp1: rx and tx mux calculation
Merge branch 'premerge'
uhd: added the concept of installer path (along with local path) for
package data
usrp-e: misc code tweaks
Merge branch 'next' of ettus.sourcerepo.com:ettus/uhdpriv into
usrp_e_merge
uhd: add space to multiline string so quotes in the string cant disturb
the multiline quotes
usrp-e: building off of next branch
Merge branch 'next' into usrp1
Merge branch 'next'
Merge branch 'master' into usrp1
usrp-e: added gain group property
Merge branch 'usrp_e' of ettus.sourcerepo.com:ettus/uhdpriv into usrp_e
usrp1: added firmware to images makefile and prebuilt fpga images
Merge branch 'next'
uhd: windows path escape fix
usrp2: template pick rate to avoid compile errors
uhd: docs on building and installing images
usrp: rethrow validate subdev spec errors with additional info
uhd: replaced tx continuous app with tx waveform app (siggen example app)
uhd: added image utils code to search the images paths for image files
Merge branch 'master' into usrp1
usrp1: images for usrp1, makefile checks for image generation dependencies
uhd: work on tx waveforms to make it more accurate
uhd: tx waveform change how error is measured
uhd: tx waveform generates on the fly now
uhd: removed msvc warnings and errors (no M_PI)
Merge branch 'master' of ettus.sourcerepo.com:ettus/uhdpriv into usrp_e
basic: better errors for invalid antenna selection
usrp: added get dboard iface to simple wrapper, and set gpio debug to
dboard iface
Merge branch 'master' of ettus.sourcerepo.com:ettus/uhdpriv into usrp_e
usrp-e: added dboard iface set gpio debug call
usrp-e: fixed codec control gain calculation error, added tx policy
registers, set to next packet
uhd: convert types corrected for little endian, created SSE2 float/short
conversion for no-swap case
usrp-e: implemented tx policy and handling of async messages
usrp2: changes to mux calculation routine and usrp2 fpga compat number
Merge branch 'convert_types' into mux
uhd: switched the IQ order interpretation for convert types
Merge branch 'mux'
basic-tx: mirror the rx subdevices for basic tx boards as well
basic-tx: added docs for new subdevices
Merge branch 'next' into usrp1
usrp1: codec pga gain control fix
usrp1: swapped the mux values to account for the convert types routines
usrp1: cast enum to char before printing as %c
usrp1: handle special dbsrx clocking case
usrp1: some app notes
usrp1: add the 4rx image to the installed usrp1 fpga images
Merge branch 'usrp1' of ettus.sourcerepo.com:ettus/uhdpriv into usrp1
Merge branch 'pps_test' into next
Merge branch 'next' into usrp1
uhd: fixed short conversion (IQ swap) and added test between short/float
uhd: added interleave/de-interleave type conversion routines
Merge branch 'convert_types' into usrp1
usrp1: subdev spec tweaks and docs
usrp1: work on gpio clock divider for dbsrx, still not locking
usrp1: init the subdev specs so they will be non-empty
usrp2: flush the error flow messages, issue the stop before register
configure to align count
uhd: sine table for tx waveforms
Merge branch 'next' into usrp1
usrp1: flush for flow error messages
usrp1: Fedora sdcc note and change fw error to warning (find should not
error)
usrp1: tested dbsrx, works with lower divider
Merge branch 'ise12' into next
Merge branch 'usrp1' into next
Merge branch 'usrp1' into next
Merge branch 'usrp1' into next
usrp1: added docs and author
usrp: dboard eeprom burner app takes slot param (fixed for automatic)
usrp: test for async messages, also renamed pps test
usrp2: added some pps docs using the test example app
uhd: added enable flags for usrp1 and usrp2
Merge branch 'master' into usrp_e
usrp-e: typo fix for ad9522 regs size
usrp-e: configure flag option for usrp-e support
usrp2: provide clock over mimo connector so usrp2 can share refs
uhd: added single usrp interface, added usrp1 properties to prop names
usrp1: implemented multi-channel dsp control of shift freq
usrp2: make usrp2 dsp multi-channel compatible
uhd: honor the LIB_SUFFIX option, added docs for LIB_SUFFIX and tweaked
other docs
usrp1: reworked the io_impl for usrp1 to use the vrt packet handler
usrp1: multi-channel rx working, modified vrt handler to deinterleave
usrp1: multi-channel tx working, modified vrt handler to interleave
usrp1: sanity check, only 1 channel per tx slot
basic: added the 4th BA subdevice to basic and lf dboard code
libusb: various minor code tweaks
libusb: various minor code tweaks
usrp1: fixes to remove warnings and errors for usrp1 + libusb windows
Merge branch 'xusrp' into libusb_win
usrp1: modified control to use the c++ ifstream over fopen
usrp1: removed msvc warnings for usrp1 impl code
usrp: modified pps input tester to use double with real value for seconds
Merge branch 'xusrp'
Merge branch 'libusb_win'
usb: moved msvc stdint file and changed cmake conditional for msvc
Merge branch 'master' into usrp_e
usrp-e: updated dsp for multiple shift properties
usb: tweaks to usb code to cleanup properly and/or in error conditions
usb: work on libusb code to use a single context across all calls
usb: zero copy work, multiple endpoints with single context, async io
usb: disable thread interruption on wait calls
usrp1: add print out messages when loading images
usb: added some documentation to wrapper base
usb: use the proper libusb include (in path set by pkgconfig)
uhd: fix warning by adding brackets for while(cond){};
usrp1: filter the discovery routine on the serial
usrp2: application notes for the LEDs
dboard: better warnings for invalid IDs and invalid ID combinations
usrp1: modify fpga file load to use read (readsome seems to not work here
in windows land)
usrp1: move the get handles call into the for loop scope to facilitate
decontruction
Merge branch 'master' into libusb
wbx: fix for id swap typo
usb: submit should return ssize_t, usrp1: set hash before reset after fw
load
Merge branch 'libusb'
usrp1: fixed compile time warning, tweaked fw load message
usrp: transfer resize options and documentation
usb: added libusb docs to build guide, usrp1: moved transfer param docs
usrp: added get codec rate to dboard iface
usrp1: replace byteswap with htonx (it was wrong to just swap)
usrp: added subdev enabled property
usb: set rt thread priority for the libusb event loop
uhd: implemented recv timeout for zero copy interface
Merge branch 'tvrx_uhd'
uhd: updated AUTHORS and README for tvrx and usrp1
Merge branch 'master' into usrp_e_next
usrp-e: update to build with the master
usrp-e: untested attempt at zero copy iface for mmap
usb: catch open errors and print message, device: catch exceptions at
discovery time
uhd: print system info on library load
Merge branch 'next'
uhd: implemented a double timeout (in seconds) for send and recv chains
uhd: reworked the zero copy interface
uhd: implemented udp zero copy asio with async calls
uhd: changed buffer allocations to be in a single chunk, udp: pass frame
sizes into the impl constructor
udp: added io service work to keep service running
usrp2: removed extra print-outs in init
uhd: modified tx timed samples to deal with timeout
Merge branch 'timeout' into usrp_e_mmap
usrp-e: implemented mmap with new zero_copy timeout work, added much
debug verbosity
Merge branch 'usrp_e_mmap' of ettus.sourcerepo.com:ettus/uhdpriv into
usrp_e_mmap
uhd: added include for enable_shared_from_this when used
uhd: bounded buffer pop sets back element to empty to decrement references
Merge branch 'timeout' into usrp_e_mmap
usrp-e: check if flags are ready after poll
timeout: proper way to check for timeout in full buff mode
usb: added dummy usb implementation for building without usb (throw, not
segfault)
uhd: replaced frame params for the zero copy interfaces with a device
address
uhd: transport docs for UDP and USB (moved from usrp docs)
usb: moved event handler thread into the zero copy interface
Merge branch 'master' into next
udp: fixed boost format syntax for warning message
usrp-e: implemented the USER_PROCESS flag and CTM poll technique
usrp1: use the transport frame sizes to calculate the max spp
Merge branch 'next' into usrp_e_mmap_b2
usrp-e: use frame size to calculate the max samples per packet
usrp2: moved samples per packet calculation into io_impl
usrp1: ensure that the current buffer was committed before getting a new
one
uhd: tweaked docs/notes on transports
tvrx: converted floats to doubles to avoid msvc warnings
udp: implementation for blocking recv w/ timeout, switch async
implementation w/ #define
udp: fix msvc errors for udp transport
udp: worked blocking send back into udp transport, enable async with
#define
udp: add docs note about the udp transport
Merge branch 'subdev_enable' into next
tvrx: added enabled prop to set and get
usrp: added calls to get subdev and mboard canonical names
uhd: better warning message for failing to set rt priority
usrp: comments for set subdev spec in single usrp
uhd: fix async msg test to reflect new timeout api
usrp2: implement fc seq number on tx header packing
usrp2: add fc control registers, use small timeout for control packets
again
usrp2: implemented flow control monitor
usrp2: use 32-bit flow control sequence numbers
usrp2: use select rather than manually polling the simple udp socket
usrp2: enable the cycles per ack, and drain recv without the timeout
(fixes previous conflict)
Merge branch 'dbsrx_clock_div'
Merge branch 'set_bandwidth'
uhd: test eob ack message, usrp2: remove rx drain on init with the
promise of a reset register
usrp2: register overflow, underflow, and pps level for pic
usrp2: increment tx sequence after commit
usrp: test async messages app randomly runs tests
usrp2: added docs on flow control ricer args and using usrp2 with a switch
udp: fix to use concurrency hint, default hint is zero when no async
enabled
usrp2: handle destination port unreachable icmp in fw (kills streaming
and update packets)
uhd: fix docs on boost version, also add additional version string for
1.44
usrp2: move udp port initialization into mboard impl so its done before
async registers are setup
uhd: removed 1 sample buffers in test async messages
Merge branch 'flow_control' into flow_ctrl
Merge branch 'flow_ctrl_with_fpga'
usrp2: temp fix to send dummy packets and flush so FPGA vita machine are
in known state
usrp2: dont need to start streaming for this hack
usrp2: make the booty smaller than the number of recv frames
usrp: created multi-usrp (multi chan, multi board), and deprecated
mimo-usrp
usrp: moved warnings logic into wrappers
Merge branch 'master' into flow_ctrl
usrp: deleted deprecated simple and mimo wrappers, moved implementations
into headers
multi-usrp: corrected calculations for channel and mboard indexes
uhd: made ticks signed in time spec, fixed full secs implementation,
added unit tests
uhd: split unit tests into individual tests by file + they get installed
multi-usrp: fixed num channel calculation, moved logic to cpm functions
Merge branch 'multi_usrp'
usrp: change the bandwidth param to a double (its a frequency), add set
and gets for BW in the wrappers
uhd: remove some warnings in MSVC and with typo in xcvr2450
usrp: updated docs to reflect switch to multi-usrp interface
usrp: added docstrings to single and multi usrp for undocumented methods
uhd: added name parameter to gain group, get range, set/get value by name
usrp: added gain element access by gain name to multi and single wrappers
usrp: use the dboard id to prefix the subdev gain group names
usrp: convenience wrappers for dealing with overall gains
usrp: use a dash as the gain name prefix separator, removed RX/TX auto
suffix for XCVR board cnames
usrp: remove irrelevant copied comment from single usrp
usrp2: handle real overflow packets in host, reload continuous stream
cmd, remove firmware handling
Merge branch 'master' into flow_ctrl
Merge branch 'usrp2_overflow' into flow_ctrl
usrp2: fw sends gratuitous arp on link-up
Merge branch 'garp' into flow_ctrl
Merge branch 'flow_control_fpga' into flow_ctrl
images: remove exe bit left by some build processes
dbsrx: reject asymmetric clocks (odd divisors)
Merge branch 'master' into flow_ctrl
dbsrx: allow for setup time after changing the vco selection
created ascii art dft plotter in uhd
uhd: created tune request struct and implemented more fine grained tuning
calls
fix copy/paste typo piroundable
uhd: tune helper + request, forgot to use and set target freq
uhd: doxygen comments, moved enum comments, added to metadata for all
entities
usrp: rework lo offset logic to use bandwidth, add test case
usrp: fixed validate subdev spec typo for empty string cases
uhd: replaced print warning with a post warning call and registry
uhd: moved templated dict implementation into ipp file
Merge branch 'next' into usrp_e
usrp_e: fix to get compiling with next branch
usrp: added a time sync check for multi usrp
usrp: added to subdev spec comments/docs
Merge branch 'usrp_e' into usrp_e_next
Merge branch 'ue1_rev2' into usrp_e_next
usrp_e: added support for building fpga image into images Makefile
usrp-e: implemented fpga loading and compat checking
usrp-e: use clock control to get clock rate, removed temporary constant
Merge branch 'next' into flow_ctrl
uhd: added rx to file example, simplified cmake file for examples
uhd: added rx samples to udp example, cleaned up other examples, added
gain options
uhd: removed dilv in rx files examples
Merge branch 'next' into usrp_e_next
uhd: added to python module check macro, move check to lib dir
uhd: change python module check descriptions to use words
usrp2: documented LED E
Merge branch 'next'
Merge branch 'master' into flow_ctrl
uhd: added dict get method, used in usrp1 image loading
uhd: fixed typo - removed export for templated class
usrp: created mboard eeprom map class, implemented for usrp2
images: remove exe bit left by some build processes
Merge branch 'garp' into good_stuff
Merge branch 'ovfl' into good_stuff
usrp2: implemented mboard eeprom into usrp2 mboard
Merge branch 'good_stuff' into mb_eeprom
usrp2: move mboard eeprom instance into iface to the clock control can
access it
usrp: print eeprom key/value pairs in the probe app, fixed mac addr size
usrp: replaced device specific burner apps with one generic one for
mboard eeproms
usrp: implement name checking on dicovery (all platforms), separate usb
serial from serial (for now)
usrp1: pulled in cmake build system for usrp1 firmware
Merge branch 'good_stuff' into mb_eeprom
uhd: dont check for python interp if PYTHON_EXECUTABLE specified
uhd: rename identifier for usrp1 eeprom, and fix offsets, add serial
support to usrp2
uhd: for eeprom writeback, write and set only those values changed
uhd: created docs for the device naming, command usage in usrp2 docs,
removed redundant docs in usrp1
Merge branch 'mb_eeprom'
usrp2: added notes about 3rd party sd cards to docs
Merge branch 'dbsrx2'
dbsrx2: removed windows warnings, made bandwidth param a double
usrp2: led F documentation fix
Merge branch 'master' into flow_ctrl
usrp2: implemented clear state for RX and TX control, and zero sample
command support
added warning about rfx classic boards and dboard notes
usrp_e: use the transport to calculate the max spp (with a fix to init
the xport first)
Merge branch 'master' into usrp_e_next
usrp-e: check the return code on system call, also removes warnings
usrp_e: renamed directory to usrp_e100 to reflect product name
usrp-e100: renamed files and classes in usrp-e100 to e100 name
usrp-e100: moved kernel header to lib dir, remove the header check,
default enable to false
usrp-e100: add header path for the utils directory as well
fixed string constants find and replace typo
uhd: reorganized utils cmakefile to use list of sources
usrp-e100: added empty eeprom for eeprom get property
Merge branch 'master' into usrp_e100
usrp1: usrp1 util is conditionally enabled
uhd: renamed enums to reflect new convention
Merge branch 'master' into usrp_e100_i2c
usrp-e100: implemented wrapper for i2c device node + ioctls, implemented
e100 eeprom map
usrpbbbbbbbbbbbeeeeeeeeeeee fix typo
uhd: created a meta range that is a range of ranges for gains and freqs
uhd: added meta-range clip and implemented in dboards, fixed step
calculation
dbsrx2: updated code for ranges use
uhd: made unit test for meta range and fixed bug
usrp-e100: split vendor/device field for eeprom, rename fab rev to model,
fixed char cast (to treat like integer)
Merge branch 'usrp_e100_i2c' of ettus.sourcerepo.com:ettus/uhdpriv into
usrp_e100_i2c
usrp_e100: added byteswapping calls to vendor and device (its NBO)
usrp-e100: add serial and name checks to the usrp-e100 discovery routine
uhd: pulled in some worthwhile changes from flow control branch
usrp2: switch the timeout to units of seconds
Merge branch 'ranges'
usrp2: fix discovery timeout, use default
Merge branch 'master' into usrp2p
usrp2: made enums for the rev types and implemented in code
usrp-n: populated name properties to use the generated cname from iface
uhd: fixed ranges stuff, export symbols and use doubles not iterators...
uhd: removed windows warnings, added string formatting in usrp-n
usrp-n: renamed docs and burner app, added burner app documentation
usrp2: fix ip addr eeprom offset in motherboard eeprom parser
Merge branch 'public_master'
usrp: use a spawn thread to ensure that a pirate is spawned before
continuing (fixes lockup issue)
uhd: added printable to string methods to ranges
uhd: ranges symbol fix, try extern macro
udp: added polling alternative to select for mac
uhd: git diff
uhd: added to printable string methods for ranges
uhd: tweaking the export template instance macro
Merge branch 'mac_fixes' into ranges_fix
Merge branches 'master' and 'master' of ettus.sourcerepo.com:ettus/uhdpriv
uhd: new versioning scheme with API compat number
usrp: removed deprecated interfaces simple and mimo
Merge branch 'master' of ettus.sourcerepo.com:ettus/uhdpriv
usrp2: ms didnt seem to like unlocking an unlocked mutex
uhd: added printable to string methods to ranges
uhd: new versioning scheme with API compat number
usrp: removed deprecated interfaces simple and mimo
Merge branch 'flow_ctrl' into next
usrp_nxxx: software workarounds for weird power up state
fpga: performed a forceful checkout of fpga to overwrite with current
fpga code
Merge branch 'fpga_ise12' into fpga_next
Merge branch 'usrp_e100' into next
Merge branch 'fpga_next' into next
usrp-n210: added fpga build entry to images makefile
usrp-n2xx: modified fw build name in makefile
uhd: added new hardware to readme
Merge branch 'next' of ettus.sourcerepo.com:ettus/uhdpriv into next
usrp-e100: updated for building with next
Merge branch 'fpga_flow_control' into next
Merge branch 'refclock_docs'
packet_router: created nearly empty router with eth in attached to mapped
memory
packet_router: connected and created CPU read from interface (slow path
in place)
packet_router: created inspector and added dsp output (however inspection
logic does not enable it yet)
packet_router: created com signals (device IO lines that may be ethernet
or serdes)
packet_router: added all input/output signals to module, created the comm
muxes (in and out)
packet_router: some tweaks, dsp output routing seems to work but has
wrong offset
packet_router: collapsed inspector states, fixed terminology for cpu inp
vs out
packet_router: fixed swapped connection typo, dsp tx routing works
packet_router: added lines for com crossbar and com output mux
packet_router: created dsp framer for rx path
packet_router: used registered valid signal for BRAM read cycle delay
packet_router: swapped comm mux for a crossbar, serdes crossbar out now
muxed into the comm output
packet_router: removed unused status words from readback mux
packet_router: use control register bit for master mode flag
packet_router: use BRAM enables to perform pipelined reads
packet_router: renamed inspector output signals and connected (for now)
to cpu, dsp, crs
packet_router: added splitter and mux for slow path stuff (also fixed
typo in crossbar input)
packet_router: registered control flags, added clear to all state machines
packet_router: fixed sof bug for cpu (== 1), some logic tweaks, added
debug
packet_router: added a way to program in the ip and mac addrs, and added
inspector check
packet_router: transplanted the async error interface, its now sent into
the packet router to be muxed to com out
packet_router: implemented crossbar and valve module, moved sreg into
router module
packet_router: moved dsp framer into a module, added clr to splitter and
renamed
packet_router: moved udp tx proto machine into packet router, replaced
udp_wrapper in top level with some fifo conversion stuff
packet_router: mux the crossbar input after the protocol framer
packet_router: program the dsp udp port and ip addr through setting
registers
packet_router: it makes more sense to connect the control flags this way
now
usrp: replace struct member sizeof with this macro so it compiles on mac
packet_router: modification for sequence number and vrt header offset
usrp2: cover both rev3 cases for usrp2 revision numbers
packet_router: split the control register into misc, cpu hs out, cpu hs
inp
packet_router: added status readback for mode, incremented compat number
uhd: added read-back calls to dboard iface gpio settings, and optional
mask
usrp2: added docs page for usrp2 that points to nxxx page
usrp-n: some rx path fixes
Merge branch 'dboard_iface_gpio'
uhd: added macro to enable/disable components
uhd: set the HAVE_USB_SUPPORT FALSE when not found (fixes error)
uhd: tweak configuring usb messages
uhd: tweaking the explicit instantiation stuff, just aesthetic
uhd: added template macro to ddl import as well (macos)
usrp: move dsp tuning wrap-around into the dsp utils (allows the dsp
handler to get the full value)
usrp-n: set ad9777 mod mode to transmit above nyquist of DSP
uhd: only enable C when we are building the USRP-E100 utilty apps
uhd: only install usrp2 apps when the component is enabled
zpu: added a zpu + wishbone opencore and integrated into top level
zpu: shrank the ram size and address bus to 16k
zpu: brought status signal out to top level
zpu: moved stack pointer and made connection for status
zpu: set all the address widths to 16, grumble
usrp-n: simplify ctrl response error so it cant throw, also increase
timeout while we are at it
usrp2: polished the multi-device addressing scheme and updated docs
Merge branch 'fpga_ise12'
packet_router: renamed top level files in an attempt to merge cleanly
Merge branch 'ise12' into packet_router
packet_router: gave the inspector a 4th output which is CPU only
packet_router: added fifo before cpu_out, tweaked inspection logic
packet_router: raise enable for bram reads the cycle before as well
usrp2: provided way to disable flow control updates by setting to zero
usrp2: pretty much gutted the buffer pool stuff with other misc changes,
not in working shape
usrp2: implemented packet ctrl to read and write slow path packets from
the new interface
usrp2: removed buffer pool macros and constants from memory map
usrp2: replaced spi and i2c async stuff with sync (since were out of the
fast-path)
usrp2: remove non-relevant buffer pool things from memory map
usrp2: implement routing mode calls, and prefix pkt ctrl calls
packet_router: filter on dest ip addr and bcast mac addr
packet_router: enable the serdes and always send GARP
packet_router: take that back and only garp when link is up (FIXME
initial state before garp call)
packet_router: added helper functions to packet router, added clear,
fixed handshake, garp at start
packet_router: split control transaction for commit into two lines
packet_router: implemented code to program the addresses into the router
packet_router: dont register mac, also reorganized some tidbits
packet_router: added sregs for ip addr and ports
usrp-n: removed serdes control, its not needed, fw must set this up
packet_router: added cpu input and output control registers, modified
control code
packet_router: incremented fpga and fw compat numbers
usrp-n: configure clocking over the serdes cable
usrp2: configured clock delay over mimo cable
usrp2: set time over serdes when slave, added constants to top of cpp file
added docs for mimo cable usage
packet_router: added control register to set the udp control port
packet_router: reverted enable change to dsp framer, it was already
correct
packet_router: harmless logic tweaks
zpu: moved top level file in hopes for easy merge
Merge branch 'packet_router' into zpu
usrp-n: created cmake/zpu build for firmware
zpu: added blink lights to usrp2
packet_router: all non ip/udp should also go to both
packet_router: reject icmp dest unreachable when port does not match
usrp2: added clocking notes to mimo cable docs
Merge branch 'fpga_ise12'
usrp2: update images makefile for moved fpga top level code
usrp2: added mimo_mode address arg and documented it
zpu: working txrx, modified blink lights to look better, no interrupt
(poll handler)
zpu: working, modified top level sizes, disable interrupt
Merge branch 'zpu' into next
Merge branch 'packet_router' into next
Merge branch 'zpu' into next
usrp2: replaced hal interrupt with NOPS, removes warnings
usrp2: removed auto* stuff (except usrp2p) and added to readme and authors
usrp2: updated images Makefile for the zpu gcc compiler
Merge branch 'dsp_tune'
uhd: use the option function for the components
usrp2: removed mb linker stuff, added bootloader + rmi gen
usrp-n210: integrate zpu and packet router, builds but untested
usrp-n2xx: moved perifs out of 0-16k to +20k to not intersect with a
virtual cpu address space
usrp2: added support in fw for setting dsp0 and err0 ports with protocol
framer changes
usrp2: pulled some changes from the next branch to make merging easier
usrp2: brought err0 transports into device and mboard constructors
usrp2: removed alignment buffer and implemented event based recv +
alignment, TODO test me
usrp1: negate the rx cordic reg word because things were inverted and
nobody noticed
udp_ports: set the source port and destination port from table
udp_ports: set the source and destination ports
udp_ports: host code tweaks, seems to be closer to working
usrp-n210: almost working w/ packet router + zpu
usrp-n210: delay reset for boot loader stack pointer to init, copied
bl.rmi without debug
usrp-n210: removed fw warnings, bootloader does full size 16k load
dbsrx: increase setup time for dbsrx band select
uhd: implemented top-level component registry
uhd: use the include subdir macro to simplify the lib subdirs cmakelists
udp_ports: fixed address comparison B+14 is comparison
usrp-n210: add missing wires, incr compat, use boot ram as stack space
udp_ports: added message handling to alignment code
usrp-n2xx: corrected memory map weirdness, disable verbose in net common
udp_ports: enable async recv in xport, set performance params in top
level, things working
uhd: fixed component registry function
Merge branch 'udp_ports' into next
Merge branch 'master' into next
Merge branch 'udp_ports' into next
usrp2: got fw working on usrp2+nseries (crosses fingers)
zpu: renamed the directory for the usrp2 fw to zpu to reflect the cpu type
fw: edit readme, removed old files
Merge branch 'fpga_next' into uhd_next
usrp2: print mimo master/slave mode on init
usrp-e100: added check for linux when configuring
cmake: changes to finding python interp, some other tweaks
cmake: moved module files into modules directory, set modules path
cmake: disable the in-tree build prevention
packet_router: use the mode register to reset hs control and cpu sms
packet_router: code tweaks, renamed instances of buffer pool, removed
unused ctrl reg
Merge branch 'fpga_next' into uhd_next
Merge branch 'uhd_master' into uhd_next
cmake: fix typo in setup python interp
image: make the build rules depend on deps so they ensure the directory
exists
Merge branch 'master' into next
packet_router: replace buffers interfaced in packet router with
buffer_int2
packet_router: change router control for buffer_int2
usrp2: remove ram macros from memory map, conditionally load fw update
usrp2: removed extra print ip functions
usrp2: removed unused changed signal for mode selection
Merge branch 'fpga_next' into next
uhd: use -B option on python to prevent generation of bytecode files
udp: tweak warning on socket resize
usrp2: remove temp power up state hack, it seems to be fixed
usrp2: implemented get time last pps
usrp2: what the hell, why does that make a difference
uhd: removed SOB always from tx examples,
usrp2: zpu compile flags use -phi, -abel is obsolete
usrp: xcvr dboards should also register their default subdev name as 0
xcvr2450: update comment for full duplex case
usrp-n210: checked in updated bootloader (from next with fixes)
usrp-n2xx: use init non zero constant (see fixme), also simplified spi
flash read size functions
usrp2: fixed mdelay (used ticks rb register), cool led blink in u2init,
removed unused files
uhd: create a find packages module for docutils, cleaned up some of the
other find package stuff
uhd: potential fix for explicit template + llvm
uhd: try to neaten up the attribute macros in config.hpp
uhd: created buffer pool to allocate aligned memory, and implemented in
transports
uhd: some tweaks to buffer pool
Merge branch 'cordic_policy' into next
Merge branch 'cordic_policy' into next
Merge branch 'buffer_pool' into next
uhd: added new convert directory with type conversion registry (needs
testing)
uhd: removed REQUIRED from find package calls to libusb and docutils
uhd: switched the unit test to the new convert API, implemented in vrt
pkt handler
Merge branch 'convert' into next
uhd: removed convert types, replaced by convert
uhd: renamed and tweaked some of the convert files
uhd: replaced templated ranges with one range thing using doubles only to
avoid trouble with compiler portability
uhd: increment api compat number
uhd: added get and set methods to dictionary to make swigging it easier
usrp: fix multi_usrp address documentation
uhd: added convenience factory functions for clock config
(external/internal)
uhd: update copyright dates
uhd: added python program to fix copyright years from git logs
uhd: created sensors value, made lib/types and moved files
uhd: split types into multiple files as it was getting unwieldy
uhd: fix copyright years on new files
uhd: integrated boost split or tokenizer into source files, remove string
split from algorithms header
uhd: create sensor value from string
packet_router: tweak mode SR (its only 1 bit)
usrp2: tweaking firmware
usrp: change wording on pps error message in multi usrp
usrp-n2xx: remapped the front panel LEDs for firmware
usrp-n210: firmware changes related to init and bootloader
usrp-n210: use cpu rst on the wb+icap, uploaded latest bootloader rmi
usrp2: eth addrs, wrong type, should be bool
usrp2: firmware pad bins to zero to deal with optimizing out the static
vars that init to zero
usrp2: removed cruft and bitrot apps from fw
usrp2: replaced pad argument to gen bins macro with a setting variable,
simplifies code
usrp2: fw print addrs fast path fix
usrp-n210: uploaded most recent bootloader rmi
usrp: removed old includes that didnt need to be there
usrp-n210: added power-on-reset controller, reset all wb perifs
usrp2: restart read before mode switch, added comments
xbar and valve: fix switching delayed by active signal
uhd: added findgit to the repo in case older cmakes dont have it
uhd: use internal() to default clock configs, dont use PPS_INT, theres no
such thing
uhd: add msvc stdint.h so we can use stdints typedefs normally like, fix
in fw_common.h
uhd: replace all the instances of float not pertaining to io types with
double, simplifies life
uhd: removed unused/forgotten file
uhd: use double for seconds in example apps so we can do partial seconds
uhd: changed convert routines to return the function pointer
uhd: fix size param error when getting a convert routine in pkt handler
usrp2: clock_sync_delay_cycles adjustment for the image size
usrp1: implement soft time ctrl for send at, recv at
usrp2: calibrated mimo clock delay for n210 (same as usrp2 classic)
usrp2: different clock delays for usrp2 and usrp-n210
usrp2: use the mac address to determine serial# for older usrp
uhd: moved fix-co-years and added path option
uhd: update copyright dates on host code
usrp2: update copyright dates on firmware code
usrp1: added docs on missing and emulated features
uhd: tweak component macro for build system
uhd: more useful prints for component macro
uhd: make static block safe with a try,catch,print
uhd: tweaks that make macos happy
uhd: renamed test directory to tests to be consitent
uhd: drop a digit from the api compat number (1000 is plenty)
usrp-e100: added readbacks for time now and time pps
usrp-e100: added readback mux 32 as slave 7 for time readback
usb: use thread interruption in usb zero copy on deconstruction
examples: init metadata with time before loop begins
usrp1: work on usrp1 hardware compat with the api
Merge branch 'usrp1' into next
uhd: added set debian arch when building images, may remove warnings on
dpkg install
usrp1: set eob on md when shutting off receiver, because we can
Merge branch 'fpga_next' into uhd_with_fpga_next
uhd: limit the git log to 1 entry when extracting version info
uhd: removed deleted fpga files removed from fpga repo
uhd: fix CPACK_DEBIAN_PACKAGE_ARCHITECTURE
Merge branch 'next'
uhd: correct msvc terminal commands for building
uhd: change constants to doubles for BOOST_CHECK_CLOSE
uhd: use doubles as the theta when calculating the sine table
uhd: added error code print to benchmark
udp: shrink default recv_frame_size by 4 bytes until FPGA handles 2 byte
pad correctly (1516)
usb: restored disable_interruption on get_lut_with_wait (gets called
externally)
Merge branch 'fpga_fix'
udp: revert depadding hack for recv_frame_size
usrp-e100: changes to regs map for re-mapping of address space
usrp-e100: added misc test register 32 bits
usrp-e100: created component for stand-alone usrp-e utils and added wb
test util
usrp-e100: so far internal vco code works w/ 64mhz
usrp-e100: working clock control 61.44, 52mhz
usrp-e100: clock control use boost math gcd for divider calculation
usrp-e100: work on clock control
usrp-e100: remove unused clock control constants, enb test clock
Merge branch 'multi_usrp_only' into usrp_e100_devel
usrp-e100: added app notes for fpga loading and reclocking
usrp-e100: tweaks to clock control and setting from api
usrp-e100: work on clock control
usrp-e100: combined clkconfig and fpga downloader into usrp-e-utility,
simplified code
usrp-e100: changes for global reset and non-zero sids on rx
uhd: added docs on usrp2/n, removed empty n2xx doc page, misc
usrp1: changes that make benchmark rx work
usrp2: added to the doc notes on communication problems
usrp-e100: added 32bit test read/write register, fixes to get building
uhd: fixed maxosx bug, was resizing the transport buffer
usrp: rename special_props to have a unique prefix, and typedef it in
dboard iface
uhd: use boost typedef for scoped_lock
Merge branch 'macos'
Merge branch 'iface_swig'
uhd: added missing API export for special props
uhd: if_addrs check that iter->ifa_addr is NULL before continuing
udp_zero_copy_asio: removed the #ifdefed num frames and min buff size
stuff
Merge branch 'udp_xport_work'
usrp-e100: added missing newfifo files to list, added missing signals for
timed
usrp-e100: added passthrough to images makefile, tweaks to usrp-e-utility
usrp-e100: reverted clockgen config + tweaks, its working
usrp-e100: tweak for clock control register calculation, works better
usrp-e100: revert compat number until its ready
usrp2: dont set the time for slave devices, they always take from mimo
cable
uhd: remove single usrp (leave a typedef), multi-usrp is a superset now
uhd: implemented high-res get time in time_spec_t
uhd: use time spec get_system_time to simplify soft time control
uhd: simplify the mach time usage based on example from web
usrp: added set and get master clock rates to usrp API
uhd: replaced sdev and single usrp in examples with usrp and multi usrp
usrp1: fix for tx disable on EOB
usrp1: added to emulated features docs Transmitting a specific number of
samples
uhd: added some minor images docs for E and N series
usrp1: removed binds and sptr allocs in usrp1 io impl
uhd: reusable buffers for libusb zero copy implementation
uhd: fix typo in ref vector docs
usrp-e100: replaced safe managed buffers in usrp-e100 mmap with custom
ones
usrp-e100: use pre-bound get send/recv buffers in io impl
Merge branch 'multi_usrp_only' into convert_fc64
uhd: added io type and conversion for complex64 (its not really useful)
Merge branch 'multi_usrp_only' into latency_test
uhd: cleanup for latency test
Merge branch 'convert_fc64'
Merge branch 'latency_test'
uhd: various performance tweaks
udp: simplfy zero copy asio overhead with less shared_from_this, and
timed waits when not needed
uhd: work to remove dynamic allocations of std::vector in
vrt_packet_handler calls
uhd: change bounded_buffer implementation and code using it
uhd: removed instances of shared_from_this() in transports
usrp2: fix for icmp echo reply checksum (data was not included in
checksum)
usrp2: pre-bind the get buffers methods on init so its not in fast-path
uhd: replace asio buffer in make safe w/ memory and length, makes things
simpler
usrp-e100: notes on unbricking/clock reovery
Merge branch 'fpga_next' into usrp_e100_devel
usrp2: fix for lingering packet problem
uhd: potential fix for macos asio recv issue (just disable it)
usrp2: initialize _ctrl_seq_num to remove many valgrind warnings
udp: removed asio implementation, created custom managed buffer classes
to re-use
uhd: replaced std::vector<type> for buffer arguments in send/recv
uhd: tweaks for windows warnings and errors
uhd: tweaks to vrt pkt handler and usrp2 fc monitor
Merge branch 'master' into next
udp: comments and minor code tweaks for udp zero copy impl
Merge branch 'usrp_e100_devel' into next
uhd: increment api compat number for changes in next branch
uhd: tweaks to bounded buffer
uhd: use ref vector class for the conversion routines I/O
uhd: simplified converter calls in vrt pkt handler with ref vector changes
udp: udp_zero_copy_asio comments and tweaks
uhd: reference vector fix revealed when building w/ debug
uhd: set BOOST_SP_USE_QUICK_ALLOCATOR for managed buffer overhead, hope
this doesnt cause trouble later
uhd: misc speedups w/ look up tables
uhd: tweak for io type size table code
usrp: added mboard param to get time now and last pps
uhd: third iteration of the reference vector
usrp2: speed up for alignment logic, replace std::list with some bit
shifts
usrp: added sensors props to mboard and subdev (removed stupid = 'char'
thing)
usrp: added get sensors api to multi usrp for rx/tx subdevs and mboard
usrp: implement sensors in all the dboards, deprecated read rssi and get
lo locked
uhd: added to_<type> calls to sensors to make it easy
packet_router: added support for two dsps into router
uhd: work on identification docs, moved duplicated notes in general
uhd: added arch flags for sse2 (was not implicit on x32)
uhd: optional variable to specify a non-default name for uhd library
uhd: tweaks for windows msvc compiler warnings and errors
Merge branch 'master' into next
uhd: boost linking + msvc configurable, defaults to static
uhd: use source properties to set flags and defs not globally, but only
for the source
added port_sel param to dsp framer
uspr2: memory map tweak for dual dsp
usrp2: added 2nd dsp support to firmware for 2 and N series
usrp2: prefix the dsp and ctrl registers with 0 in preparation for 2nd dsp
uhd: work on multiple dsp in host wrapper
Merge branch 'sensors' into usrp2_dual_dsp
usrp: support for multiple dsps in props and implemented in usrp1
uhd: got all compiling w/ changes, changes to channel calculation in
multi usrp
usrp2: added indexed regs for rx dsp and ctrl
usrp2: moved all dsp related code into dsp_impl and split for multiple
dsps
usrp2: lot of work on dual dsp, grep for TODOs before continuing
usrp-n2xx: reimplemented the net burner to use one socket per session
usrp-n2xx: reimplemented nicks image readback ontop of changes
usrp-n2xx: checkout burner into next branch
Merge branch 'master' into next
udp: update docs for transport, create common header for wait
implementation
udp: try non-blocking recv first for performance
usrp2: code working again in a completed form but did not test dual dsp
uhd: moved indexed device addr routines into api
usrp2: 2nd dsp working, tweaks regs map and other bugs
uhd: replace header checks in cmake files with more robust compile checks
for features
usrp2: cleanup clocks firmware stuff, removed unused code
uhd: added 9 byte serial to dboard eeprom class
uhd: simplify dboard eeprom code by passing iface into load/store
Merge branch 'sensors' into dboard_serial
uhd: switch dboard id prop to whole eeprom struct
Merge branch 'usrp2_fw_clock_cleanup' into usrp2_dual_dsp
usrp2: div->ldiv fix for overloaded types w/ msvc
usrp2: fixed flow control monitors indexing, fixed multi-usrp send bug
usrp2: move buffer resize code and add rule for bsd/mac
Merge branch 'packet_router_2nd_dsp' into usrp2_dual_dsp
Merge branch 'usrp2_dual_dsp' into next
uhd: added a bunch of custom exceptions, not used yet
uhd: moved exception to top level include
uhd: renamed the assert header to assert has
uhd: replaced instanced of std::exception with the uhd exceptions
uhd: switch algorithm namespace to uhd
uhd: exception code gen simplification
usrp-e100: conditional code for when fpga downloader is externally
included
uhd: sensors header fix to make swig happy
uhd: sensors header fix to make swig happy
uhd: make ic reg maps depend on common.py
usrp-e100: disable the global reset for now
usrp2: minor optimization, only disable interruption when we need to
wait()
udp: return the managed recv buffer to the buffer queue on timeout
uhd: make ic reg maps depend on common.py
usrp-e100: disable the global reset for now
usrp2: minor optimization, only disable interruption when we need to
wait()
udp: return the managed recv buffer to the buffer queue on timeout
usrp2: only include fw_common when needed, remove virtual send/recv, not
exposed
usrp1: check for fw images only for uninitialized devices
Merge branch 'master' into next
ethfifo_reorg: switch buffer int2 lastline to work as a length parameter
Merge branch 'mb_iface' into next
uhd: removed mb_eeprom from mboard iface (already exposed in property)
Merge branch 'master' into next
usrp2: work on mtu discovery
usrp2: firmware can send jumbo dummy packets (only writes up to 2048)
usrp2: tweak the mtu discovery logic
uhd: added missing set_tx_antenna() in tx waveforms
uhd: copied examples changes from next onto master branch
uhd: replace file_string() with string() for deprecation reasons
Merge branch 'fpga_master' into next
Merge branch 'master' into next
Merge branch 'boost_fs_string' into next
Merge branch 'usb-cancel' into next
usrp-e100: disabling VCO cal check, its not right, and the warning alarms
people
uhd: whoops, spi convenience functions have 32 bit data
usrp: dboard iface can inherit from i2c iface
usrp-e100: reinstate the VCO calibration timeout message
uhd: thread safety notes and moved some docs to general
packet_router: created packet dispatcher component to replace packet
inspector in router
fix: vita_rx_chain1 should use unit2 (since err0 uses unit1)
usrp2: comments for buffer size setting
usrp: fix for mux calculation when using real q
usrp2: save alignment indexes between state to fix the lost packet problem
usrp2: save alignment indexes between state to fix the lost packet problem
usrp: moved wrapper utils into multi-usrp
usrp2: created safe call macro and handle usrp2 ~mboard throwing
usrp2: created safe call macro and handle usrp2 ~mboard throwing
usrp1: throw in control calls that fail rather than print the error
Merge branch 'master' into next
usrp1: also replaced control error prints w/ throws
usrp1: safe destruction for usrp1 device
uhd: fixed include in safe call, added quotes for
SET_SOURCE_FILES_PROPERTIES
Merge branch 'master' into next
uhd: fix safe call header cuz it was moved on the next branch
uhd: revert changes to rx_timed_samples
Merge branch 'packet_router_2nd_dsp' into next
usrp-e100: fpga fix removed missing directory from include
uhd-images: specify CPACK_PACKAGE_FILE_NAME so files names are platform
independent
usrp-e100: added module compat num check, made fpga compat constant more
obvious
uhd: only specify BOOST_SP_USE_QUICK_ALLOCATOR for the lib, apps can be
built without it
usrp2: bump up timeout on mtu discovery (seen to be a bit too small on
windows vbox)
uhd: created tx_samples_from_file.cpp and added to rx_samples_to_file.cpp
uhd: a lot of tweaking, new parameters, and sig handler for to/from file
examples
uhd: added continuous streaming and new options to tx_waveforms
uhd: offer alternative named for python binary (seen on ubuntu server)
uhd: cleanup/tweaks on timed samples examples
uhd: created rx_multi_samples for multi-channel example
usrp2: also store expected_time in-between states
uhd: make CMAKE_BUILD_TYPE a visible variable in the gui
usrp2: clip the mtu discovery if its within default MTU + a few
usrp2: minor fix to use more ntohl
Merge branch 'windows_fix' into next
usrp2: fixed mtu discovery bug, was using the last failed value
usrp2: common memory map, define slave bases in different headers
usrp2: moved sregs in fw memory map, new framer register table
usrp2: moved sregs in host code, simplfy reg struct a little
usrp2: use the proper lwip macros to set the ip header
simple_gemac: fixed typo for tx_clk and tweaked ethtx_realign.v
usrp2: cleanup checksum code and fix precompute checksum bug
memory_reorg: new bootloader.rmi for n210
usrp2: use new and common slave base map for usrp2/n210
usrp2: increment fpga and fw compat numbers
reverted zpu stack pointer change, incremented fpga compat number
Merge branch 'fpga_memory_reorg' into usrp2/new_reg_map
usb: fix callback cast in libusb zero copy under msvc
uhd: added comments/documentation to clock_config
usrp2: use the discovered mtu to clip the user specified mtu
uhd: setup cpack components for component based installers
uhd: setup UHD_VERSION and CPACK_PACKAGE_FILE_NAME
uhd: work on debian package requirements in cpack setup
uhd: added libusb1 to CPACK_RPM_PACKAGE_REQUIRES
uhd: try to be smart when setting up cpack when UHD_PACKAGE_MODE=AUTO
uhd: update copyright headers with automated script
Merge branch 'fpga_master' into n200_support
uhd: added USRP-N200 build support to images Makefile
usrp2: modified firmware build rules to chain the dependencies (better
for make -j4)
uhd: work on mac osx packaging
usrp2: fix typo, now building n200 fpga images
usrp2: fixed serial bootloader for N series
usrp2: created net burner gui wrapper for N series
usrp2: added usrp_n2xx_net_burner_gui to build system installation
Merge branch 'fix/usrp_n2xx_serial_bootloader'
Merge branch 'mac_packaging'
Merge branch 'usrp_n2xx_net_burner_gui'
uhd: work on versioning technique for the releases
uhd: swapped UHD_PACKAGE_MODE with UHD_RELEASE_MODE (boolean)
uhd: various packing fixes (lib suffix, and library components)
uhd: expand UHD_RELEASE_MODE setup to all debian and redhats
uhd: set LIB_SUFFIX automatically (all 64-bit redhats)
uhd: revert VERSION setting for libuhd, macosx does not like patch level
usb: changes to allow for static linking of libusb on windows
usb: tweaks to the build guide (libusb + windows)
usrp-e100: set the ticks-per-second every time we change clock rate
uhd: remove build information in the version string (just
major.minor.patch)
usrp1: ignore claimed interfaces, avoids the problem of discovery when
one device is claimed
usrp1: switch usrp1 iface to use spi read (transact never worked)
usrp1: reverted spi transaction changes to the usrp1 firmware (broken and
not needed)
usrp1: fixed codec ctrl aux adc read (didnt start conversions) +
cleaned-up logic
uhd: added UHD_IMAGES_DIR option to include images in the package
uhd: implemented boost barriers on all code that creates threads
uhd: install dlls into runtime path, updated docs
uhd: disable visibility=hidden on non-dll platforms (cygwin)
Merge branch 'fix/usrp1_spi_read'
Merge branch 'images_install'
Merge branch 'rfx400_tx'
Merge branch 'use_boost_barrier'
uhd: increment patch number for next release
uhd: added images and readme installer component
uhd: setup INSTALLER_PKG_DATA_DIR for windows systems
uhd: define LINUX in build system to simplify some checks
images: create a tag file to associate the version number w/ images
uhd: specify msvc for implementations known only to work on msvc
usb: newer libusb1 does not need to link with setupapi.lib
uhd: set CPACK_PACKAGE_INSTALL_DIRECTORY on NSIS so we dont get an
inconsistent version suffix
uhd: a few minor changes to get uhd building under mingw or cygwin
uhd: replace <prefix> with <install-path> in docs for clarity
uhd: tweaks for cygwin/mingw, always link winsock2, findusb1,
__USE_W32_SOCKETS
usrp2: ran 2to3 on python apps and make corrections for old imports to
work
usrp_n2xx_net_burner: remove thread from gui
usrp_n2xx_net_burner: working on python3 (string is not the same as bytes)
usrp2_card_burner: change the padding string to bytes
usb: mark libusb callbacks with LIBUSB_CALL to ensure correct calling
convention
usrp2_card_burner: decode byte strings into ascii for parsing
usrp2: restore executable permission on python scripts
Merge branch 'python3_work'
uhd: always link winsock2 on windows, disable pthread SCHED_RR for cygwin
Merge branch 'mingw_cygwin'
usrp1: fix path to firmware files for fpga top level
usrp-e100: reset dboard clocks on rate change, and dont cache in dboard
iface
usrp2: support fw protos with older compats for various parts
uhd: attempt to cleanup language in thread prio warning
usrp2: add check for holler protocol, we can support backwards
usrp2: use the firmware's discovered compat number
Merge branch 'fix/usrp_e100_clock'
Merge branch 'thread_prio_warning'
uhd: python messages more verbose + print boost configuration info
uhd: specify the UHD_PKG_DATA_PATH once (since images shipped w/ drivers)
uhd: only set UHD_BUILD_INFO on successful return (also removed unused
cruft)
uhd: use int() casts on enum constants to help swig2 parse it as int
uhd: move thread loop condition flag to before barrier (prevents race
condition)
uhd: added more hw params to rx_ascii_art_dft
usrp1: rmmod usbtest because it interferes
uhd: added scoped lock to device find and make (for thread safety)
usrp: work on dboard_manager to register an ID for multiple xcvr
combinations
usrp: support for grand daughter board eeprom
xcvr2450: initialize the max_power variable
wbx: split wbx into daughterboard and granddaughterboard implementation
Enhance WBX IQ balance performance through LO drive
Merge branch 'sbx-adi'
Merge branch 'gdb_support'
uhd: updated readme for WBX/SBX work
usrp1: the rx mux was reversed (fixed multi-channel rx)
usrp1: fix for tx under remainder conditions
rfx: reverted change, now prefer R divider to clock divider
usrp_e100: added recv/send_frame_size xport args
uhd: added option for nsis installer to set PATH
rfx: changes to pick from the dboard clock rates and use R=1
uhd: use UHD_PKG_DATA_PATH environment variable to override the one in
constants
usrp2: improve the compatibility error messages
Merge branch 'rfx_use_clock_divider'
Merge branch 'usrp2/discover_with_old_fw'
Merge branch 'usrp2/discover_with_old_fw'
uhd: use UHD_PKG_DATA_PATH environment variable to override the one in
constants
uhd: removed constants.hpp.in, replaced w/ per source compile defines
Merge branch 'master' of ettus.sourcerepo.com:ettus/uhdpriv
usrp2: use default mtu as upper limit unless user specifies
uhd: fixed typo in tune request/result inter_freq -> rf_freq
usrp-e100: add ability to set/get default master clock rate from EEPROM
USRP1: added support for setting clock rate from EEPROM
usrp-e100: shrink name field to git mcr into eeprom
Merge branch 'master' into next
uhd: use int() casts on enum constants to help swig2 parse it as int
uhd: switch vita unpacker over to using proper vita length
dbsrx: implement SUBDEV_PROP_ANTENNA to give users a better error
usrp2: include dd.exe in windows installers
usrp2: card burner protections when the user specifies a device not in
the list
uhd: make benchmark example take a rate, and give special warning for
usrp1
usrp2: added support for GPSDO configuration bits in EEPROM
usrp2: allow devices to be discovered when usrp2_iface::make throws
usrp2: move card burner code out of get_options so get_options can be
used by the gui without interference
Merge branch 'master' into next
usrp2: combined peek and poke commands and added virtual firmware
registers
usrp2: added the concept of device locking to usrp2/nseries devices
usrp1: toggle the FPGA reset and RX reset registers at init
Merge branch 'rfx_rssi'
usrp2: added REF_MIMO and PPS_MIMO for USRP2 clock config
Merge branch 'master' into next
uhd: work on the backend for a logging facility
uhd: added configurable default log level and thread safety
uhd: moved the logger into the utils subdir
usrp: replaced conditional dboard debug prints w/ UHD_LOGV(often)
uhd: tweaks for logger file entries
uhd: replaced many conditional prints with UHD_LOG usage
uhd: added interprocess file lock to the logger file
uhd: replaced warning post with calls to UHD_MSG(warning)
usrp-e100: removed stdio prints from implementation
uhd: removed more iostream stuff from usrp* implementations
uhd: various tweaks to log and msg, replaced a few remaining stdio
usrp1: added more logging to usrp1 iface for debugging
usrp1: overload read_eeprom to handle multi-byte reads
usrp_e100: work w/ ad9522 clock configuration
usrp-e100: added soft sync for ad9522 clock control
Merge branch 'next' into use_vita_length
usrp-e100: use misc test32 register to store fpga hash
Merge branch 'master' into next
usrp2: device locking, use gpid so the process cant lock itself out
usrp-e100: created device address arg for master clock rate, removed
eeprom hack
uhd: work on logging and message facility initialization
uhd: init log file lock ptr to null
Merge branch 'tvrx2'
uhd: add gcc warning for sign comparison mismatch
usrp1: apply conditional disables/enables to rx and tx
usrp1: correct TX codec rate, it should also read 64e6 when probed
uhd: replace managed buffer shared pointer w/ intrusive pointer to reduce
overhead
u1e: incremented compat # to 4 for vita length change
Merge branch 'next' into use_vita_length
usrp-e100: incremented compat # to 4 for vita length change
Merge branch 'use_vita_length' into next
Merge branch 'master' into release_work
USRP1: implement MBOARD_PROP_CLOCK_CONFIG, only accepts internal
uhd: some build system tweaks
usrp2: moved register map into #defines, entries for new dsp frontend
Merge branch 'master' into release_work
uhd: removed deprecated warning API, log+msg now in API
usrp2: turn on ups_per_sec to avoid timeout issues on low sample rates
uhd: picked some minor changes from super packet handler
usrp-e100: set_ignore_sync_fpga_plus_codec
u1e: incremented compat # to 4 for vita length change
Merge branch 'fpga_next' into uhd_master
Merge branch 'usrp_e100_clock_sync'
tvrx2: fix docs formatting typo
uhd: work on sync docs
uhd: notes on LO calibration, and tweaks
usrp2: added app notes on multi channel RX
uhd: added app notes to docs on tuning
uhd: tweaks to log and msg implementation
Merge branch 'gpsdo_ant_power_docs'
Merge branch 'sync_docs'
usrp2: catch exceptions thrown in locker loop (like the user unplugs
device)
uhd: pseudocode tweaks for sync docs
wbx: mixers always enabled, ant switches always defined
uhd: just send a mini EOB packet for tx timed samplesa
usrp-e100: work on aux spi
usrp-e100: added check for wishbone readback and clock recovery
usrp-e100: removed clockgen config stuff and docs
usrp-e100: bring up the clock as the first thing
uhd: increment version minor for release
uhd: many tweaks for tx_waveforms including performance
added copyrights
usrp-e100: work on aux spi
usrp-e100: make reg_test32 persistent across resets, bump compat number
usrp-e100: removed passthrough files, not needed w/ aux spi for clock chip
usrp-e100: fix message typo, its master_clock_rate
uhd: added safe call on a few dboard related deconstructors
uhd: added more SAFE_CALL macros to hardware wrapper dtors
uhd: added information in reference sources to sync docs
usrp: added registers and mux calculation for fe work
Merge branch 'usrp_e100_aux_spi' into frontend_work
uhd: changed compat numbers to reflect dsp work in fpga
e100: dual dsp support (compiles, not tested)
usrp: use dboard name A or single slot boards
e100: dual dsp working, cleanup for io impl, needs more testing
e100: disable debug prints in io impl
udp: replaced callbacks in zero copy interface by giving direct queue
access
uhd: made all bounded_buffer methods forced inline
sph: added unit test for overflow handler
uhd: added host to/from worknet conversion to byteswap header
e100: bug fix w/ SID parsing (endianess)
uhd: allow benchmark to continue on untracked error codes
usrp1: moved fx2 control into its own directory
uhd: added scaling factor to conversion routines
uhd: supper packet handler support squashed
usrp2: super packet handler support squashed
usrp1: super packet handler support squashed
usrp_e100: super packet handler support squashed
uhd: removed vrt packet handler code
uhd: fix some warnings under msvc in sph
uhd: update packet handlers when the clock rate is changed
uhd: fix for resize routine of super packet handler
usrp_e100: init the subdev specs before calling io_init
uhd: under/over flow app notes
Merge branch 'fpga_next' into uhd_next
uhd: updated images Makefile
b100: added b100 firmware (squashed)
b100: added b100 host (squashed)
b100: added images to Makefile
n2xx: makefile typo fixes
uhd: increment version minor for release
uhd: added host to/from worknet conversion to byteswap header
b100: support for dual dsp
b100: tweaks to get dsp branch working
Merge branch 'master' into frontend_work
uhd: tweak for bounded buffer pop elem
e100: removed usrp from directory prefix
Merge branch 'master' into next
e100: clean up gpio wrapper stuff, fix order of setup in make()
usb: fix for fx2_ctrl include issue
b100: fix fx2_ctrl include to use relative path
Merge branch 'philip/e100-fpga-test-fixes' into next
b100: removed usrp prefix from files
b100: update find to match usrp1 style + features
uhd: increment version minor for release
usb: fix for fx2_ctrl include issue
uhd: created benchmark rate app
uhd: added dropped samples calculation to rx test
uhd: more benchmark tweaks, removed old benchmark rx
b100: removed defunct test utilities
Merge branch 'next'
uhd: use aligned loads and stores for floats in sse2 conversion routines
Merge branch 'benchmark_rate'
USRP2/N2x0: incremented compat numbers for frontend work
usrp2: removed asserts in card burner, remove ascii decode
fw_updater: windows enumeration works
usrp2: macosx fix, use object's strip, not str (could be unicode)
uhd: replaced boolean for thread loop w/
boost::this_thread::interruption_requested
N210: update burner for python3.0, added listbox for device selection in
gui
Merge branch 'card_burner_tweaks'
Merge branch 'fw_updater'
uhd: replaced boolean for thread loop w/
boost::this_thread::interruption_requested
uhd: re-worded the fast-path thread app notes
e100: implemented spi, i2c, messages w/ peek/poke
b100: also spi wait before using spi to ensure its ready
e100: wrong gpio, its 147 for interrupt
e100: tweak which I don't understand
uhd: on e100, this benchmark control thread should also have prio so it
can spawn both
uhd: benchmark rate fix so we dont use metadata on timeout
e100: added proc_int and buffer for async messages
usrp2: fix typo w/ setting send frame size
e100: proc_int should be high when interrupted
e100: consistent name for e100 fpga files in host code and images build
Merge branch 'gps_work'
Merge branch 'wbx_v3'
uhd: added dynamic throw and clone to exceptions
uhd: print the exception so e gets used (avoid MSVC warning)
usrp2: init the usrp2_ctrl_data_t to make valgrind happy
b100: always init the serial number in find
Merge branch 'master' into next
uhd: work on templated property class
uhd: created a property tree to store properties
uhd: change for default prop create()
uhd: forgot to commit properties file
uhd: created uart iface to inherit from
usrp: created core controllers for i2c and spi on 100 series
uhd: added core for time64
usrp: created cores for the rx and tx dsp
usrp: filled in rx and tx frontend cores
uhd: fixed sse2 conversion bounds check
usrp2: work on setting up controllers
usrp2: setup many more control objects and xports
usrp: populate a tree from a subdev
usrp2: added gps ctrl and mboard and gps sensors
usrp2: restored discovery and most of io_impl
uhd: re-work to make the properties easier to use
usrp2: fix for new props interface
usrp2: init subdev specs and tick rates
usrp2: filled in missing TODOs and code cleanup
usrp: got probe working w/ the new property tree
usrp: fixed core bases (miscalculation)
uhd: work getting multi-usrp working
uhd: added properties unit tests, use shared ptr<void> in tree
uhd: loopback working on usrp2
usrp: filled in the to pp string method
uhd: properties tweaks and docs
uhd: make sure things are initialized
uhd: implement prop tree usage in utils
usrp: deleted a bunch on obsoleted files in usrp directory
uhd: misc tweaks and also msvc compile
usrp2: moved impl back into usrp subdir
b100: got b100 into the properties tree like usrp2
b100: removed old impl files, moved async processing to io impl
b100: some tweaks (unresolved streaming issues ATM)
b100: made async callback safer, other tweaks (still issues)
usrp2: restored component registry
b100: figured it out, endianess was set wrong
e100: moved e100 into property tree, probes ok...
e100: removed unused files from e100 build dir
e100: added false alarm count + sleep for gpio irq (since its shared)
e100: disable eeprom read so double open can work for now
usrp1: implemented properties interface on usrp1
usrp1: removed unused files from impl dir
usrp: moved fx2 stuff into common folder
uhd: replaced alignment indexes implementation w/ boost bitset
usrp: added validate_subdev_spec to all io_impls
usrp: created common code to demux an rx stream (b100, e100)
usrp: updated documentation for various changes (mimo mode, subdevice
spec defaults)
usrp: renamed sma source option to external
usrp: renamed ref_source to clock_source (terminology)
usrp1: tweaks + implemented other features to mimic async and inline
messages
usrp: removed register defs in regs.hpp that were covered by cores
usrp2: split compat number into major/minor (increment minor for fixes)
usrp2: restored fpga compat check, updated for major/minor scheme
usrp2: set the set_alignment_failure_threshold to match default socket
buffer size
usrp2: accept old db name 0 for backwards compat
uhd: added inline message testing to the messages example
usrp: handle frontend swapping if the first subdev is QI or Q
usrp: added clipping to link max rate when setting sample rate
usrp: enable/disable frontends when validating subdev spec
Merge branch 'master' into next
Merge branch 'next' into properties
usrp: fix error message typo in recv_packet_demuxer
uhd: added subtree capability to property tree
usrp: added software scale factor adjustment
uhd: benchmark example will print help if no rate specified
uhd: added unit test for properties subtree
Merge branch 'b100_shrink' into next
Merge branch 'fpga_next' into next
uhd: moved modules and some other files into cmake subdir
uhd: updated the major and minor versions for next branch
b100: fix for fpga syntax error on xfer_rate
Merge branch 'fpga_next' into next
Merge branch 'next' of ettus.sourcerepo.com:ettus/uhdpriv into next
e100: use the USRP_E_READ_CTL32 ioctl for async msg read
e100: typo fix for calling ioctl on iface
uhd: some tweaks to fix msvc warnings
usrp2: added a place for product code in eeprom map
usrp2: added a place for product code in eeprom map
uhd: added tasks to simplify thread spawning use cases
uhd: pulled misc changes from other branches into master
uhd: created SSE2 conversion routines for fc64
uhd: some header changes from next
udp: squashed the wsa work and added documentation work
usrp2: use the err transport for tx/err, and rx xports are recv only
usrp2: added fw minor and moved ICMP dest error handling to txrx app
Merge branch 'master' into next
uhd: tweaks for windows boost 1.47 compile
usrp2: try/catch for socket open on discovery, use large send buffers
windows
udp: check for FastSendDatagramThreshold + print warning inside the wsa
transport
uspr1: shutdown thread in deconstructor (not automatically)
Merge branch 'b100_shrink' into new_work
b100: fix for fpga syntax error on xfer_rate
fpga: print timing report after generate bin file
usrp2: split inspection logic into each relevant cycle
usrp2: comment out poll + print overflow/underflow in fw
fpga: squashed new_work fpga changes onto uhd next
Merge branch 'new_work' into uhd_next
fpga: save the N2XX bit files into the images build
uhd: images build script chmod recursive, files only
uhd: fix for images CMakeLists.txt to use the new modules directory
uhd: add get_tree call directly to the device
uhd: forward declare property tree in device so gnuradio swig cant
complain
usrp2: workaround for older boost thread sleep
usrp2: use the command function from card burner for net burner ifconfig
usrp: update multi usrp header to use complete subdev specs
uhd: added get_version_string and way to disable system info print
uhd: replaced boost filesystem path with fs_path in property tree
uhd: added helpful UHD_VAR macro for debugging purposes
e100: perfer orc if available and dont build neon intrinsic support
uhd: fixed some warnings with gcc on macosx
uhd: exit task on the catch-all exceptions, and dont print anything
usrp2: fix unintended change in last commit
uhd: make spawn barrier a member of a task (see notes)
usrp2: created new gpio core and used in dboard iface
usrp: use a new cmd bit to signal stop
usrp2: fixed swapped tx/rx signals for nsgpio
vita_rx_ctrl: use an extra cmd bit to signal stop
usrp2: bump minor version number for changes
usrp2: remove old unused readback mux value
time64: reverted mimo sync changes to time64
usrp2: remove hw config readback, not needed
usrp2: adjusted mimo delay cycles for FPGA changes
usrp2: turn that message into an exception, require at least 7.1
Merge branch 'atr_fix_fpga' into atr_fix
usrp2: shutoff streaming using the stop bit (fix)
uhd: incr minor, add date to images tag, add package target to makefile
uhd: added print constraints to makefile, and used directory variable
uhd: minor tweak for send_packet_handler, force zero sample send hack to
return zero
uhd: specify all the boosts
uhd: if found, require a liborc version orc-0.4 > 0.4.11
usrp1: fix for multi-channel, OTW channel width is always 1
usrp1: handle special case of no rx or no tx dsps
uhd: fix sync docs typo for pps detect method1
udp: only build WSA transport for MSVC (not supported on mingw for
example)
uhd: also find RST2HTML_EXECUTABLE as rst2html.py
usrp2: always resize socket send buffer to size of SRAM (we will never
commit more)
usrp2: bump usrp2 fw minor to 4 for upcoming patch release
N2x0: delay ADC A inversion so A and B are latched in the same
N2x0: added a Makefile to build all N2x0 projects (make -j4)
N2x0: print constraints summary from makefile
connect unused BRAM inputs to 1s to save routing logic
usrp2: bump FPGA minor number to 2 for patch release
uhd: bump patch version to 2 for upcoming patch release
e100: continuation of the atr fix to get e100 to build
Merge branch 'fpga_patch_release' into patch_release
uhd: added readback of version and arbitrary string property to probe app
usrp: dboard sensors fix, populate for tvrx, and should be empty on
basics/unknown
uhd: replace cast in usrp_burn_mb_eeprom to be like other apps (fixes
ubuntu 10.4 compiler bug)
usrp: use the frontend BW to clip the overall tune range
usrp2: initialize channel occupancy variables,
usrp2: manually deconstruct tasks, fixes cleanup bug
usrp2: reconnect frontend calibration, timing meets
fpga: minor tweaks to build system
uhd: fix for dealing with negative wrapping in time_spec
fix warning on dat_o in atr_controller16.v
e100: squashed work on bus implementation on GPMC
usrp: preserve sub-ranges when calculating overall tune range
Merge branch 'fpga_patch_release' into patch_release
uhd: bump minor version for patch release
usrp2: manually deconstruct tasks, fixes cleanup bug
uhd: fixed formatting on gpsdo doc, added time sync docs on mimo cable
uhd: more doc tweaks and added gpsdo notes to index
uhd: tweak for tx_timed_samples to pad async msg timeout
uhd: also normalise the time spec when adding/subtracting (added unit
test)
uhd: added docs on FPGA images for n-series hw revs
usrp2: made iface deconstructor safe (unlock can throw)
usrp2: made iface deconstructor safe (unlock can throw)
Merge branch 'patch_release'
Merge branch 'fpga_master' into next
e100: changes to support bus work
e100: only generate random _even_ sizes for loopback
e100: changed compat numbers, and tweaks
e100: reimplemented loopback for easy regression testing
e100: add FIFO clear and kernel clear to loopback
uhd: removed WSA UDP transport implementation
uhd: fill in other fields of pkg-config file
xcvr2450: fix the locking at marginal frequencies
e100: use model string to determine FPGA image to support E110
Merge branch 'fpga_master'
e110: added support to images Makefile
usb: removed handler thread, do work in get buffer calls
usrp1: reset control objects in this order to avoid race conditions
usb: reimplement ~libusb_zero_copy_impl to avoid segfaults and indefinite
timeouts
Merge branch 'fpga_master' into e110_support
Merge branch 'e110_support'
uhd: remove Boost_LIBRARIES from pc file libs.private
uhd: updated docs usb post-install, added uhd-usrp.rules
uhd: add mimo cable config option to rx_multi_samples
e100: fix FPGA filename lookup, and use model string for name
udp: added check_registry_for_fast_send_threshold to non-wsa transport
wbx: fix bug in wbxv3 tx gain readback calculation
n-series: removed unused bootloader files in fw
usrp: fix check for max stream_cmd.num_samps, upper 4 bits reserved
usrp: remove wax::obj entry point (not used)
uhd: updated to images documentation
usrp: fix string mapping for PPS_NEG clock config
usrp: also use the new API to get the property tree in multi-usrp
uhd: separate_device_addr, copy globals across entire address
usb: added interface args to usb abstractions
b100: order of deconstruction, kill marauder first
usrp1: disable pad to one for usrp1 (not needed)
usrp: super packet handler release in order
uhd: bumped version numbers for this new cycle
uhd: doc tweak for udp transport notes
e100: added support for r4 differential clocking
e100: added ref locked sensor for clock reference
usrp2: uart/udp work in host and fw, working
usrp: add gps control to the API
gps: use absolute timeout for communication
e100: added support for internal gpsdo
e100: gps uart deal with cr and nl
usrp1: copy regs files into common and fix include paths
Merge branch 'fpga_master' into uhd_master
e100: gps talking -> termios magic foo
images: typo fix building B100.bin
e100: tweak for codec params for slight improvement
Merge branch 'uhd_master'
usrp2: allow backwards compat with previous fw
images: include hash in the generated file name
usrp2: remove old pre-release warning
usrp2: give users a warning for gpsdo support + fw update
images: fix makefile for E1XX build dirs
gen2: fixed rate calculation when > 128
e100: codec control register fix for tx
uhd: help messages for user on rx samples to file
usrp: added revision field to the dboard id class
usrp: added product and revision fields to eeprom
b100: add reference lock sensor
uhd: specify range on tx_waveforms --ampl
connect and map b100 and e100 front-panel leds
Merge branch 'fpga_master' into uhd_master
usrp: add documentation for front-panel leds (needs FPGA update)
b100: new eeprom map for special 9 byte serial
uhd: added supported models and some doc tweaks
uhd: added post/pre un/install scripts for deb and rpm packages
uhd: added missing shbang to pre/post scripts
b100/e100: additional constraints for clock rate configuration
b100: perform test claim on usb before continuing
usb: improve messages/logging for when the usb open fails
nseries: added dont check rev option to the burner app
docs: unified gpsdo docs and sensors stuff
uhd: change how we configure version.cpp
uhd: more doc tweaks to build guide
usrp2: fix typo in top level core files
32 bit compat number for E and B series
forgot to add gpio atr to makefile source list
uhd: added toolchain file for native arm neon build
uhd: bump verion compat to 3.3.1
basic/lf: keep dboard clocks disabled (should be by default)
n2xx: set default for checkrev on burner so gui still works
uhd: allow device addr (from string) to parse empty values
uhd: moved wax API into deprecated files
uhd: removed unsed interfaces, deprecated otw and io type
uhd: work on streamer interface, lots of docstrings
convert: reworked convert to use new identification standard
convert: restored unit test functionality
uhd: created backwards compatible send/recv implementation
uhd: restored super packet handler functionality
uhd: lots of work releated to streamer work and usrp2 implementation
usrp2: additional corrections for streaming to work
uhd: tweaks to streamer interface and multi-usrp convenience interface
uhd: updated examples to use new streamer interface
usrp1: did work for stream interface on usrp1
uhd: restore io type header for swig backwards compat
uhd: device_deprecated.ipp typo fix
uhd: renamed some of the stream types and functions
usrp1: multi channel receive working
usrp1: type conversions and 8-bit work
usrp1: various tweaks related to streaming
usrp2: work on alternative OTW formats
usrp1: got the 16Msps working (needed non hb-filter image)
uhd: added one packet mode to rx streamer
usrp1: support variable clock rate through API
b100: performed streamer API update to b100 impl
e100: performed streamer API update to e100 impl
uhd: renamed convert markup to format
usrp: deprecated clock config, added time/clock source calls
uhd: fixed 8sc item32 converter on head/tail cases
uhd: added trailer parsing for occupancy
uhd: added converter for item32 as cpu type
uhd: changed stream args args to device_addr_t
uhd: added some stream docs/app notes
usrp: added get_tx/rx_rates
usrp: add api control for tx/rx dc offset control
usrp1: implement rx dc offset control hooks
usrp: add api call to adjust phase/mag imbalance
usrp: update frontend cores for dc offset
usrp: register properties for correction and dc offset
usrp: prefer name iq_balance for api call
usrp: docs tweaks and renames to multi-usrp
usrp: placeholder for potential set_next_command_time call
usrp: reorganize frontend paths in tree for correction stuff
usrp: added called to query bw range as well
somebody made a typo
usrp: multi usrp API tweak
usrp: fix rate calculation logic
usrp2: reg map change for GPIO core
e100/b100: moved gpio regs and compat readback
e100/b100: init tree before filling it
increase vita rx fifosize to 10, like USRP2, make things work
uhd: performance speed up for tx waveforms, no iterative libmath per
sample
convenience makefiles for top level projects
usrp: parse rx stream args scalar
remove unused irq to meet timing
uhd: performance speed up for tx waveforms, no iterative libmath per
sample
uhd: fixed compilation error on tx waveforms
usrp: work on dboard code to use subtrees to populate frontend props
rfx: setup frontend property tree for rfx dboard
basic: disable dboard clocks by default
sbx: squashed Ben's SBX work
wbx: squashed Ben's WBX work
sbx: bring SBX into the tree
wbx: bring WBX into the tree
wbx: fixed typo because it should tx
uhd: bumped version number for next branch work
uhd: modify examples to use new time/clock source API
usrp2: fix channel mapping calculation
uhd: dont pass 0 sample buffs to converter (avoid segfaults)
uhd: removed wax and props utils
Merge branch 'fpga_master' into uhd_next
Merge branch 'uhd_next'
uhd: useful tweaks from user
usrp1: fix typo when calculating rx_dc_offset register
usrp: added missing include for weak ptr
uhd: first stab at calibration app
uhd: performance improvement for tx waveforms using integer table lookup
uhd: updated ref sensor checks for new option names
need more umph out of correction values
uhd: basically usable cal sweep for wbx
usrp: basically working iq cal on tx
uhd: convert should use register_bytes_per_item
uhd: simplification for tx waveforms
uhd: lots of tweaks for calibration utility
uhd: created rx IQ imbalance app to parallel tx
Merge branch 'fpga_cal_work' into calibration
uhd: share more common code in cal utils
convert: made conversion functions into classes so they can keep state
convert: added table conversion routine for sc16 to floats
convert: simplify table conversion with templates
convert: added table conversion routines for sc8
usrp: fixed default initialization of iq bal correction
uhd: fixed sc8 table conversion, and simplified shifts
convert: msvc warning fixes for sc8 table gen
uhd: added tx dc offset calibration + tweaks
uhd: different interp methods for IQ vs DC
uhd: work on doxygen comments for stream args
convert: move priorities to implementation, different for arm
Merge branch 'convert_work'
convert: added generic conversion for sc8 wire -> sc8 host
uhd: added freq options and common gain setter
uhd: added calibration usage app notes and renamed apps again
uhd: support for applying cal corrections B100
uhd: more common code in cal utils
e100: added self-cal support with minor speedups
Merge branch 'calibration'
uhd: fixed mboard detection checks to the cal utils
basic: fix basic db center freq to always zero
usrp: clear dsp when making new streamer
dbsrx: set initial freq and bw filter after clocks enabled
b100: tweaks for fpga resets on init
uhd: tweaks to calibration utilities
usrp2/nseries: restored clock/serdes readback
uhd: fix so MSVC client apps dont rely on min/max
Merge branch 'fpga_master' into uhd_master
usrp1: set scale factor after setting converter
Merge branch 'uhd_master'
uhd: work with stream clearing
usrp: rx dsp move init code into clear (like tx)
uhd: added wireformat to samples to file
uhd: some more notes on calibration utils
uhd: correct images docs for ZPU support
usrp: added mboard param to set time next pps
uhd: update udev rules, replace SYSFS w/ ATTRS
uhd: make use of TEMP_FAILURE_RETRY when select()
usrp: better error message when dboard fails in init
uhd: typo fix for the error print
uhd: use more recent udev rules format
tvrx: fixes for tvrx since the property tree work
tvrx: adjust returned lo freq to compensate for negative cordic shift
usrp1: fixed swapped sign on rx cordic
usrp1: fix div ratio for interp register
basic: minor fix for copy paste typo
uhd: network device discovery -> calc bcast addr under certain conditions
usrp2: use the socket to determine the device addr
usrp2: created network relay example app
usrp2: more work on relay app and sequence error detection
usrp2: added bind option to the relay
usrp: added underflow_policy to tx streamer args
Merge branch 'network_foo'
uhd: manually calculate bcast addr, boost version buggy
uhd: manually link into pthreads here
e100: better error message for eeprom model error
uhd: fixes that make uhd compile on freebsd
uhd: typo fix in tx waveforms options
usrp2: fw fix for hal_uart_getc_noblock return code
usrp1: initialize tick_rate prop (fixes readback)
sbx: fix dboard tuning to cache result
usb: updated FindUSB1.cmake for standards compliance
usrp: compensate for other sc8 conversion gain
usrp: db manager tweak for contructor throwing
n2xx: updated bootloader to latest build in uhd master
n2xx: fix burner print if bad rev
Merge branch 'fpga_master'
uhd: dont populate requires.private in pc file
b100: bumped fpga compat number for slave fifo mode
uhd: patch to support PKG_LIB_DIR per debian fs standards
usrp1: use fixed bit width integer for hash
images: include license file into image tarballs
uhd: flush transport for new rx streamers
usrp2: firmware should reset dsp on icmp pkt
usrp2: same change but to fw updater
uhd: add samples per pkt option to rx streamer
usrp1/b100: handle longer reenumerations with loop and timeout
dsp rework: u2_core test implementation
dsp rework: renamed dsp signals for frontend IO
dsp rework: implemented dsp changes for other top levels
usrp1/b100: reenumeration loop with timeout only when found
dsp rework: integrated custom dsp module shells
dsp rework: top level fixes B100/E100
dsp rework: moved scale and round into ddc chain
dsp rework: added double buffer interface to vita tx
dsp rework: increase the number of effective bits in the duc scale factor
dsp rework: integrated dspengine_8to16, some tweaks
dsp rework: work on 8 to 16 engine (usrp2 ok)
dsp rework: finished engine HEADER_OFFSET stuff, add post_engine_buffering
uhd: branch-less round for time spec convert to ticks
uhd: implement convert_sc8to_sc16 table w/ scalar
dsp rework: implemented new scalefactor in rx dsp core
dsp rework: work on scaling and args parsing on RX and TX dsp
gen2: added user setting regs api and user core
dsp rework: tx trailer, scaling work (peak)
dsp rework: paramaterize post_engine_buffering
dsp rework: account for no sid used in tx vita pkt
b100: bump compat numbers for slave fifo mode
Merge branch 'slave_fifo_rebase' into dsp_rework
dsp rework: register the sample in vita tx ctrl
dsp rework: custom engine module for rx/tx vita chain
b100: sc8 mode not implemented error
uhd: updated sync docs for current API
dsp rework: work on usb wrapper for smaller packets, large luts
dsp rework: rehash of the custom module stuff and readme
dsp rework: move setting address of format register
dsp rework: added otw mode for benchmark app
b100: connect all clears for gpif
b100: delete some unused registers from map
b100: timing constraints on GPIF lines
uhd: added/renamed various readme files
b100/e100: unify rx/tx fifo clears into one
dsp rework: pass vita clears into dsp modules, unified fifo clears
dsp rework: implement 64 bit ticks no seconds
dsp rework: implement 64 bit ticks, no seconds
uhd: added sc8 conversion tests
uhd: better quantization check for convert test
e100: loopback test fix after register tweaks
windows: do not set process wide priority from thread prio
uhd: added sse2 conversions for fc64 to sc8
uhd: added sse2 conversions for fc32 to sc8
uhd: fixed orc conversion fc32 to sc8_item32_be
uhd: fixed sse2 conversion fc32 to sc8_item32_be
uhd: various tweaks for compiler warns and valgrind
b100/usrp1: various tweaks for compiler warns and valgrind
dsp rework: pass enables into glue, update power trig, parameterize, fix
module inc
dsp rework: full-rate pipelining in vita tx deframer
uhd: add over-the-wire option to tx waveforms
usrp1: big endian compile fix, conversion should cast to unsigned
dsp rework: minor simplification in vita_tx_deframer
uhd: inline time spec accessors for minor improvement
dsp rework: minor fix sph, set has time spec for tsf only
b100: added transport flushes and moved around reset code
b100: reset/reenumerate fx2 for bad endpoint state
b100: use frame boundary to calculate frame size
uhd: added async md user payload and common utils
dsp rework: added flusher to vita tx chain on clear
dsp rework: added flusher to vita tx chain on clear
dsp rework: fix dspengine_8to16 to handle padded packets
dsp rework: fix for vita occ trailer packing
Merge branch 'fpga_next' into next
Merge branch 'next'
uhd: added -fvisibility-inlines-hidden
vita rx: trigger clear after packet tranfer
usrp2/nseries: added churn to meet timing
Merge branch 'fpga_master'
usrp2: changed download url for dd.exe
usrp2: added retry logic to control packets
usrp2: some tweaks to the device locking logic
usb: added /opt/local to libusb search path
usrp1: fix advertised samples per packet in send streamer
usrp1: fix to use the db connection type to determine DAC sign
usrp2: removed unused memory map entries
uhd: fixed send pkt handler, vrt packet type was uninitialized
uhd: fixed some compile warnings for msvc
usrp: reset cordics on init after tick rate update
usrp2: device locking tweaks
uhd: fix sc16 to sc8 conversion table
usrp1: fix for cordic init, cant do it that way on tx
fpga: fix custom defs in some top level makefiles
Merge branch 'fpga_master'
uhd: added fullscale option stream arg
usrp: fix wildcard set for time/clock source
fpga: force -include_global for custom sources
Merge branch 'fpga_master'
uhd: rev iq correction numbers format
uhd: make atlbase options for msvc build
n2x0: adjustment for phase delay over mimo cable
usrp: fix from "rev iq correction"
usrp2: fw unlocks when ICMP dest unreachable
uhd: add calls to query an ABI compat string
docs: whitespace fixing usrp2 docs
Matt Ettus (714):
fixed addressing of registers, and added write enables to those that were
missing. MDIO seems ok.
Removed these files completely, they were for the old style of fifos
sort out active-low lines on locallink fifos, added debug pins
debug pins, cleaned ignores
never used, not needed
cascadefifo.v wasn't used, only the double cascade version.
fifo_2clock.v and fifo_2clock.v are empty
cleaning up the new fifos
major cleanup of 2 clock fifos
bring the testbench files up to date
made a new block ram based fifo, 64 (65) elements long, all fifos now
have "enhanced level logic" for accurate fullness. Maybe this will help...
misc ignores
set device to xc3s2000. Shouldn't make any differences.
MAC transmit seems to work now. The root cause of the problem was
accidentally using the rx_clk in one stage of the fifos on the tx side.
seems to build a decent fpga, but still some issues with a full
connection.
no longer used, replaced by newfifo version
debug the rx side
allow control of whether or not to honor flow control, adds some debug
lines
remove unused old style fifo
parameterized fifo sizes, some reformatting
Implement Eth flow control using pause frames
Untested fixes for getting serdes onto the new fifo system. Compiles, at
least
fix a typo which caused tx glitches
might as well use a cascade fifo to help timing and give a little more
capacity
More xilinx fifos, more clean up of our fifos
remove unused port
Remove old mac. Good riddance.
Merge branch 'serdes_newfifo' into new_eth
Synchronize the internal phase of the halfband filters to the start of
the "run" signal. This is important for MIMO. Bug reported by Christoph Hein
and Hanwen .
Merge commit 'origin' into new_eth
Enable pps interrupts. Not sure why they were disabled in the first
place.
Copied wb_1master back from quad radio
no idea where this came from, it shouldn't be here
Merge branch 'new_wb_intercon' into new_eth
remove unused opencores
fullchip sim now compiles again, after moving eth and models over to new
simple_gemac
Fix warnings, mostly from implicitly defined wires or unspecified widths
Properly reset the fifos. We didn't connect before.
earliest beta files renamed to avoid confusion
This branch is for porting from the quad radio, and minor text cleanups
VITA49 rx (and tx skeleton) copied over from quad radio
put 64 bit timer for vita49 on the settings bus
vita rx instead of rx_control. Ready for firmware testing. Misses
timing by a little bit, will worry later.
moved regs around for vita49
forgot to declare wires
mostly just copied over from the rx side. Still needs a lot of work.
be a little more PC about it
make the testbench work in this environment, without the crossclock
settings bus
progress on vita_tx. it compiles now, need to work on vita_tx_control.
seems to correctly deframe packets. now need to consume them.
very basic packet sending works
flag packets which arrive way too early so the device doesn't sit there
forever.
First cut at vita tx, whole thing compiles
ignore save files
fixed typo in u2_core.v resulting in unconnected net. added debug pins
Add ability to clear state out when there is an underrun
only pull from input fifo when really consuming or pushing into the next
fifo
put new setting reg into the address space in the right place
reorder the memory map
changed debug pins to see incoming data
dsp_core_tx now has setting reg base settable from u2_core. underrun bug
in vrt fixed
cleaned up the main ibs state machine
19 bit wide interface in prep for connection to UDP/IP state machines.
19-bit fifo handling for receive side of eth/udp system
barebones udp support. Compiles, but untested.
never should have checked in this generated binary file
proper time sync to pps
place udp core in the memory space
actually connect the ports -- why this isn't flagged as an error I'll
never know
typo fix
more typo fixes.
better debug pins
empty commit
make it match the 36 bit wide version
empty file, it is actually located in the control directory
debug state
forgot to declare wire
try proper reset
try a width that works...
add debug pins to find the problem with lost eof in the udp core
typo
yet more debug lines
yet another typo
should fix the endless packet bug
proper time sync to pps
allow processor to read back vrt time over readback mux
allow setting time immediately in cases where there is no external pps
input
remove time_sync and master_timer.
moved around regs, added a bit to allow for alternate PPS source
speed up timing by ignoring the too_early error. We'll need to FIXME
this later
typo caused the tx udp chain to be disconnected
just debug pin changes
Merge commit '8d19387a8642caf74179bdcb7eddf1936f473e53' into udp
copied over from quad radio
ignore emacs cruft
skeletons that don't work yet
first cut at blinking leds
builds a successful led blinker
organized the pins in the ucf by function
connect GPMC pins to debug bus
reorg pin defs
basic read support for the GPMC, responds with 16'hBEEF
block ram interface to GPMC
copied over from safe_u1e
first cut at gpmc <-> wb bridge, split u1e into core, top, and tb
wishbone bridge now with minimal functionality. Need to check
speed up the presentation of registered wb data to the gpmc
Fixed paths to help icarus find opencores and xilinx models. Added
Xilinx global set and reset module.
allow default uart clock divider
Added I2C, UART, debug pins, misc wishbone stuff
added gpio control to the wishbone
GPIOs now on the wishbone interface
Modified nsgpio.v to support 16 bit little endian bus interface.
remove the #1 delay in all the regs. They just slow down sims.
settings bus with 16 bit wishbone interface, put on the main wishbone in
u1e
place to put omap tools
first cut at automatically setting the debug pins
full neame
use our fancy new debug ports
first cut at making a bidirectional 2 port ram for the gpmc data interface
proper initialization of the ram
Merge branch 'master' into u1e
First cut at passing data buffers around on GPMC bus
ISE chokes on the pure verilog version so we use the macro
Switched xilinx primitives because they order the bits funny in the other
one
edge sync on done signals so we only fill/empty one buffer
corrected logic
loopback and test
fix syntax error which icarus allowed (filed a bug with them)
point to the new files
gpmc debug pins
invert the pushbuttons since they are active low
enable was on the wrong address pin, needs to be the highest order one
debug pins
proper flags bits
Merge branch 'u1e_uhd' of ettus.sourcerepo.com:ettus/uhd into u1e_uhd
copy in wrong place
better debug pins for going after cascading E's
more debug for fixing E's
ignore emacs backup files
pps and vita time debug pins
Xilinx ISE is incorrectly parsing the verilog case statement, this is a
workaround
bigger fifo on UDP TX path, to possibly fix overruns on decim=4
moved fifos around, now easier to see where they are and how big
connected spi pins, but the spi core still needs to be redone for 16 bit
interfaces
Merge branch 'master' into udp
Merge branch 'udp' into u1e
connect 2 clock gen controls and 3 status pins to the wishbone so they
can be read/controlled from SW
remove timescale junk
connect up the 16 bit spi core
16 bit wide spi core
preliminary registers definition
Merge branch 'usrp_e' of ettus.sourcerepo.com:ettus/uhd into usrp_e
added 16-bit wide atr controller
split out gpmc to wishbone interface to make gpmc top level cleaner
replaced ram interface with a fifo interface. still need to do rx side
lengthened delay between cycles, added more transactions on the data bus
minor changes to get it to synthesize
probably won't be using this, and it hasn't been tested
added in a loopback fifo
make timing diagrams for bus transactions. Still need to do reads
renamed to async. Will be building a sync version for GPMC_CLK
more progress on synchronous interface
more sync progress. This is just a skeleton for now, with junk content
handle all tri-state in the top level of gpmc
synchronous and asynchronous gpmc models
progress on synchronous gpmc, but it may not be possible due to the
limited number of clock edges
correct name of module
add bus error reporting
change time parameters because Xilinx IP has a 1ps timescale
async gpmc progress
async seems to work with packet lengths now. Still need to do wishbone
regs for gpmc
access frame length regs from wishbone
added pps and time capability
find time_64bit
Register outputs to omap to prevent runt pulses from falsely triggering
interrupts
Only allow new packets if we can fit the largest possible packet (2KB)
Pass previously unused GPIOs to debug pins to help debug interrupts
Merge branch 'corgan_fixes' into udp_corgan
send bus error to debug pins
separate timed tx and rx instead of loopback
have_space and have_packet now stay high even while busy,
changed comment
add timing constraints. Just have main clock signal at 64 MHz for now.
Merge branch 'u1e' of ettus.sourcerepo.com:ettus/fpgapriv into u1e
added DAC output pins, and a sine wave generator to test them
SPI passthru for programming clock gen chip on brand new boards
proper signal level for 24 bit data
switched passthru of cgen_sen_b to gpio127, made a note of it. No more
safe_u1e necessary.
allow settings bus to cross to a new clock domain, should help timing,
but not attached yet
cleaned up the logic, this is copied over from quad radio
remove port which is no longer there
Merge branch 'master' into udp
reverting logic clean up which should have made timing better, but made
it worse instead
move dsp settings regs to reclocked setting bus. Works, gets us to
within 18ps of passing timing
packet generator and verifier, to test gpmc and other data transfer stuff
Merge branch 'master' into u1e
add missing signal from sensitivity list
moved fifos into gpmc_async, reorganized top level a bit, added in crc
packet gen and test
revert commit 9899b81f920 which should have improved timing but didn't
remove files for old prototypes, they were confusing people
Merge branch 'master' into udp, removes u2_rev1, rev2
settings bus to dsp_clk now uses clock crossing fifo
better debug pins
ignores
get rid of old CVS linkage
added pragmas suggested by Ian Buckley to help ISE12 synthesis
added width parameter to avoid warnings (thanks IJB) and default value
parameter
get rid of some warnings by declaring setting reg width
Merge branch 'master' into udp
fix typo, no functionality difference
better test program for just the tx side
combined timed and crc cases. fifo pacer produces/consumes at a fixed
rate
Merge branch 'u1e' of ettus.sourcerepo.com:ettus/fpgapriv into u1e
put over/underrun on debug bus, remove high order address bits
removes the icache and pipelines the reads
send bigger packets to reduce cpu load
fix double declaration
fifo36_to_ll8 and fifo pacer need a real fifo between them or they
deadlock (by design)
test full width packets
fixes from IJB from 5/24. Basically connect unconnected wires.
experimental mods to make ram loader fully synchronous. Based on IJB's
work
change the debug pins, which makes it more reliable. This is unnerving.
Merge branch 'master' into u1e_merge_with_master
Merge branch 'udp' into u1e_merge_with_udp
Merge branch 'udp' into master_merge_take2
new files from udp branch added to main Makefile
ignore output files
from UDP branch, changed names because I want these separate from the
non-udp versions
manual merge to use localparams from udp version
non-udp uses a different address for the tx dsp core
Merge branch 'master_nocache' into master_nocache_post_merge
Merge branch 'new_ramloader' into nocache_plus_newramloader, plus manual
merge into udp version.
zero out debug pins. helps timing a little bit.
vita49 tx and rx added in, all sample rates now at main system clock rate.
assign addresses for the settings regs
use DDR regs instead of a 2nd clock
connect the rx run lines so it doesn't get optimized out
Merge branch 'ise12_exp' into u1e
use same version as usrp2-udp, so regs are same place in memory map
Phil wants gpio #145
get rid of redundant fifo18, since we can just use fifo19 and ignore the
occ bit
added little endian capability for gpmc to fifo and fifo to gpmc, since
ARM is LE.
use fifo19 not fifo18 in makefile
remove double declaration
skeleton files copied over from a dead branch
works, leds on front count up.
compiles now, added clock constraints
name build directory with ISE version name
proper name for directory
report ise version in build
allow other clock rates in vita time
Merge branch 'master' into u1e
Merge branch 'master' into u2p
debug pins
ignores
move u2_core into u2_rev3 directory to simplify directory structure and
save headaches
get rid of debug stuff to help timing
Merge branch 'master' into u2p
actually generates an image
first attempt at cleaning up the build system
proper overrun, underrun connections, debug pins.
left something out of the sensitivity list.
much bigger fifos
debug pins
produces good bin files
Merge branch 'master' into u2p
build using new build system
new core for u2p, based on u2_core
new make works on ise12
Merge branch 'master' into u2p
Merge branch 'master' into u1e_newbuild
barely fails timing on gigE/10 and gigE/12, larger fail on udp/10, but all
precompute udp checksums
added ability to clear out fifos of tx and rx.
proper dependency tracking for the makefile
Merge branch 'master' into ise12
Merge branch 'master' into u1e
Merge branch 'master' into u2p
fix bug which caused serdes fifo to disappear
Merge branch 'master' into ise12
Merge branch 'master' into u1e
Merge branch 'reload' into u1e
error packets are now valid Extension Context packets
Merge branch 'reload' into u1e
point to new location for fifos
updated tests to match new features
fix to stop endless error packets
Merge branch 'reload' into u1e
Merge branch 'master' into u2p
Merge branch 'ise12' into u2p
Merge branch 'master' into ise12
Merge branch 'ise12' of ettus.sourcerepo.com:ettus/fpgapriv into ise12
Merge branch 'ise12' into u2p
updated to ise12 fixes from main development line
remove ram loader
copied from quad radio
very slight mods from v5 version
ram_harvard2 is a workaround for a Xilinx bug that gets confused by an
unused write port on a ram
further cleanup
separate boot ram, redone memory map, connected uart
includes led blinker in bootram
attach the correct data port
reset the ack signal
moved forward from the old branch
get it to build
make loopback compile
Merge branch 'reload' into ise12
split fifo into 2 streams based on first line in each packet
mux multiple fifo streams into one. Allows priority or round robin
add mux and demux to build
remove warnings
proper selection of bank of ram for instruction, since the address
put run_tx and run_rx on the displayed LEDs
move declaration ahead of use
Merge branch 'ise12' into u2p
Merge branch 'ise12' into u1e
pushbutton now goes into interrupt controller, can be read from software.
Normally high, goes low when pushed
connect SPI to adc, correct capitalization of SEN pins
reconnect the serial clock
capitalization matching
checkpoint. New context packet generator to report underruns and other
errors
tx error packets now muxed into the ethernet stream back to the host
fix a typo
connect the demux
move the streamid so it isn't at the same address as clear_state
insert protocol engine flags when requested
this is an output file, it shouldn't be checked in
test mux and gen_context_pkt
introduce new error types
cleaner error handling
more informative error codes
sequence errors can happen on start of burst as well.
implemented "next packet" and "next burst" policies
attempt at avoiding infinite error messages
sequence number reset upon programming streamid
provide a way to get out of the error state without processor intervention
enlarge loopback fifo
checkin of generated coregen files
quad uart instead of single, for the extra on board serial ports
connect the setting reg to the real clock and reset
rx error context packets should not be marked as errors in the fifo
this is necessary for some reason
Merge branch 'ise12' into ise12_efifo_work
Matt's attempt at merging
Merge branch 'features' into ise12_efifo_merge
delay the q channel to make the channels line up on the AD9862
connect atr
Merge branch 'features' into tx_policy
attach run_tx and run_rx to leds
catch up with tx_policy
properly integrate the new tx chain
Merge branch 'ise12_efifo_work' into efifo_merge
capacity logic fix
debug pins cleanup
match the signal names in this design
no need for protocol headers since we're not doing ethernet
Clean up iq swapping on RX. It is now swapped in the top level.
clean up DAC inversion and swapping to match schematics
Merge branch 'tx_policy' into u2p_txpolicy
Use new tx_policy stuff, reassigned leds to be just like U2
Merge branch 'u1e_merge' into u1e
Merge branch 'tx_policy' into u1e
SWAP DAC A and B, invert B to match schematics
invert adc_a because it is inverted on schematic. Also clean up
extraneous
move declaration to make loopback compile
add register to tell host about compatibility level and which image we
are using
fixed makefile to compile with our new system
pins are different on rev2
updated pins to match rev2, removed dip switch, etc. seems to compile ok.
send all gpmc signals to mictor
fix timing issue on DAC outputs with rev 2. This puts the whole system
on a 90 degree phase shift
watch the ethernet chip select on our debug bus
better debug pins
allow for CS to rise before, at the same time, or after OE
fix timing problem on DAC output bus
Merge branch 'ise12' into efifo_merge_dcm
reconnect GPIOs, remove debug pins, meets timing now
separate the bootloader image into another file
revert unneeded changes and incorrect comments
checkpoint in flow control packet generation
declarations
assign setting reg addresses
add trigger to makefile
add a fifo to the end of the mux to help in timing.
go to the correct state
separated flow control and error reporting on tx path. should work with
and without flow control
typo which isn't caught by xilinx
send message on eob to ack the end of transmission
switch to 32 bit sequence numbers. Will wrap in ~15 hours at max rate
increase compatibility number for flow control
cleanup for 32 bit seqnum
proper triggering for interrupts generated on the dsp_clk
don't flag an error on eob ack
don't clear out following packets on an eob ack
now handles frames larger than the vita packet (i.e. with padding)
should combine the randomizer with flow_control
slow slew rate and lower drive to 8ma on RAM_XX signals to reduce emi
address gray coding
the width of the address bus is called DEPTH, not WIDTH...
duh
invert led signals because they are active low
fix timing problem on DAC output bus
remove old commented out code
Merge branch 'u1e' into merge_u1e
occ needs to be 2 bits wide on a 36 bit fifo interface.
need to enable both 16 and 32 bit spi interfaces -- 16 used in u1e, 32 in
u2 and u2p
u2p needs the bigger regs for some reason
reverting part of the reversion of the spi settings.
moved forward from the old branch
get it to build
checkin of generated coregen files
capacity logic fix
reconnect GPIOs, remove debug pins, meets timing now
revert unneeded changes and incorrect comments
these got dropped during the rebase
checkpoint in flow control packet generation
declarations
assign setting reg addresses
add trigger to makefile
add a fifo to the end of the mux to help in timing.
go to the correct state
separated flow control and error reporting on tx path. should work with
and without flow control
typo which isn't caught by xilinx
send message on eob to ack the end of transmission
switch to 32 bit sequence numbers. Will wrap in ~15 hours at max rate
increase compatibility number for flow control
cleanup for 32 bit seqnum
proper triggering for interrupts generated on the dsp_clk
don't flag an error on eob ack
don't clear out following packets on an eob ack
now handles frames larger than the vita packet (i.e. with padding)
fifo randomizer for emi
gray code address for emi
added ability to truly clear out the entire rx chain. also removed old
style fifo in rx.
clear out the vita tx chain and the tx fifo. need to check the fifo
handle zero-length packets properly
compiles with new file locations
reset properly
Add flow control and other small vrt fixes to u2p, minor cleanups
we're still on version 12.1
simplify time comparison to speed up logic and meet fpga timing
fix problem with consecutive timed packets on tx
get rid of extraneous U messages when we actually had an ACK
modernize the testbench
shouldn't be executable
no need for second sequence number anymore. Each dsp tx chain
packets are shorter now, so we need to tell the udp state machine that...
abstract out the crossbar functionality
packet valve. will drop incoming data if shut off.
allow any unicast packet through.
reduce warnings, modernize testbench
should safely delay the late signal which was causing timing problems
Merge branch 'time_compare_speedup' into ise12
renamed exp_pps_* to be exp_time_*, which is the mimo synchronization
signal
reimplemented mimo time transfer to handle 64 bits. Still needs
remove old raw ethernet version
udp is now the default
Only do udp now, renamed old ports to exp_time_*
slave side can now sync
time sync on usrp2 as well, added debug pins to time sync.
now supports up to 4 different udp ports
generate port number headers in the dsp error units
don't overwrite checksum values
should keep cordic spinning and the rest of the tx going through
unused line
first cut at new buffer interface for CPU. Like old buffer_int plus
reformatting
now uses 2 rams, one for read, one for write
gyrations to get it to meet timing
run should actually turn on now any time in the IBS_RUN state
processor can read back vita_time at last pps
hook up sampled pps in u2plus, remove unused priority encoder, minor
cleanups
believed to fix fifo swizzling with partially empty lines
reorganized u1e register space to make room for 64 settingregs
separate clear for tx and rx, and add a global reset from the host
sort of working latency tester
getting usable data
successful latency test. About 500 us on my laptop.
register map changes to fit in the 2nd rx dsp
clean up rx dsp and some other nets in prep for dual dsp
put these files in the right place. newfifo is long gone.
e100: integrate loopback and timed testing into main image
hook up under/overruns for debug purposes
move declarations to before use
u2/u2p: proper hookup of vita_rx_chain
u2/u2p: renamed and split some rx signals to prepare for 2nd DSP
u2/u2p: added 2nd DSP unit
u2p: 2nd DSP now in u2p as well
u2/u2p: reduce unneeded RX DSP buffering
increase compat number for double dsp change
u1e: hook up tester controls
u2/u2p: inserted short fifo into the packet inspector path to help
routing and timing
u2/u2p: shrunk ETH TX FIFO, further u2/u2p harmonization
fifo36_mux now has shortfifos on the input ports as well as output
correct port names
u2/u2p: short fifos put on both sides of ll8_to_fifo19
u2/u2p: ll8 now all active high, removed extra shortfifo from eth wrapper
u2/u2p: get rid of redeclaration
u2/u2p: packet realignment moved into the simple_gemac_wrapper19
Merge branch 'ethfifo_reorg' of ettus.sourcerepo.com:ettus/fpgapriv into
ethfifo_reorg
u2/u2p: switch over to 36 bit wide ethernet wrapper
u2/u2p: removed unneeded eth rx fifo
u2/u2p: rxdsp/cpu/err muxing now prioritizes cpu and err over rxdsp
make big tx fifo the one doing the clock crossing
u2/u2p: shortfifos in fifo36_to_ll8, no more _n junk
u2/u2p: remove duplicated short fifo
u2plus: catch up with ethfifo changes which were on u2
all: short fifos on front and back of fifo36_to_fifo19
all: removed old unused fifos
remove references to old directory
Merge branch 'gpmc_testing' into ethfifo_reorg
make fifo36_to_ll8 properly handle partial end lines.
u2/u2p: allow cpu to receive or send packets longer than the buffer size.
u2/u2p: reworked dsp framer to work more like a fifo, and do vita length
correction
u2/u2p: reworked port names on packet_router
u2/u2p: rework ports again
u2/u2p: moved dsp framer into vita_rx_chain
u2/u2p: removed redundant shortfifos from udp path (they are in the size
adapters now)
u2/u2p: enlarge dsp rx fifos to handle jumbo frames, enable in u2plus as
well
u2/u2p: fix off-by-one error in dsp_framer
u2/u2p: proper connections for dsp_framer
first cut at 36:72 and 72:36 for extra wide fifos. untested
u1e: keep up with fixes made for u2/u2p, make it compile again
u1e: removed old directory from make
prot eng should work, ethtx is a skeleton
udp: checkpoint
udp: this one adds a half line, useful on receive side
udp: this one removes half a line, used on transmit side
udp: new 32 bit wide udp state machine seems to work
udp: short fifos on prot_eng in and out
u2/u2p: reworked settings bus addresses
udp: speed up checksum calculation to meet timing
eth: add padding on incoming packets, remove on outgoing packets
moved the eth realignment stuff into the simple_gemac
eth: the danger of cut and paste
udp: fix precomputation of ip header checksum
udp: look for checksum in the right place
udp: alternate udp ports
u2/u2p: fixed instance name
u2/u2p: reorganized memory map
u2p: fixed bootloader remapping
clean up a bunch of warnings and incorrect bus widths
u1e: use icarus verilog for lint
u2p: N200 Makefile
u2p: N200 Makefile
Merge branch 'master' into next
u1e: switch to vita_rx_chain module just like other toplevels
u1e: get dsp_framer36 from u1p so it can skip the protocol header
copied over from other repo. Beginnings of a skeleton fpga image for
USRP1-Plus
compiles now
Use the 4th LED which is shared on the cfg_init_b pin
copied over from u1e, most pins hooked up.
skeleton
gpif skeletons
progress on gpif interface
added a loopback control port, will do full wishbone interface later
hook up flow control pins
use vita_tx_chain top level block
redone gpif interface to match nick's new spec
first steps to a command packet handler for u1+
constrain the gpif clock
send reset to the gpif
fix ctrl/resp path to pass all 16 bits of data instead of the bottom bit
not used
fifo to wb should be functionally complete, needs testing
put gpio back in
old and unused
successful test
give response packets the same format as tx packets
fixed length command packets
pad out packets to a minimum length
add padding into gpif response path
modernize the make files, it now compiles. not tested.
u1p: catch up with all the recent u1e changes
u1p: add clear ports to gpif, not hooked up yet
u1p: fix bus widths and other warnings
u1p: use icarus verilog to find warnings
u1p: revert change to address bus width
u1p: added loopback and timed capability just like u1e
u1p: pass tx status/error packets back through GPIF over the response
channel (short packets)
u1p: gpif-to-fx2 path should now handle arbitrary sized packets, up to 2KB
u1p: use 18 bit fifos and use full size of a block ram in the tx path
u1p:wr testbench
u1p: better way of reframing the packets
u1p: unused signals
u1p: debug pins
u1p: modernize, fix warnings, debug pins
u1p: add new file to build
u1p: modify dsp_framer36 to allow it to skip the udp prot eng headers.
u1p: should fix underrun reporting
u1p: do padding outside of gpif_rd, in packet_splitter
should split and reframe packets properly
u1p: vita packet generator for testing purposes
u1p: need to declare wires
u1p: implement a signal to indicate a partially full usb lut, to flush it
u1p: connect frames per packet
u1p: reset gpif
u2p-rebase: go back to versions on next
first cut at using lvds for adc pins
builds now
u2p-lvds: remove unused nets
u2p: FPGA internal termination on the clock line from ADC
remove old iad stuff
removed bit-rotted test harness
remove old ethernet tester, no longer needed or working
lots of renaming and moving around of toplevel directories to reflect
product names
fix copyright notice
redone DC offset with sigma-delta quantization
u2/u2p: pull IQ balance and dcoffset out of dsp_core, put in frontend
module
unused nets
u2/u2p: misc connection and compilation fixes
dsp: pass the error through in the rounding function
dsp: first cut at sigma-delta rounding
dsp: reworked round_sd, it is much simpler now
dsp: use sigma delta rounding in rx_dcoffset and in dsp_core_rx
u2/u2p: use new rx_frontend in u2 and u2p
dsp: add2_and_clip_reg and round_sd now are now strobed to be compatible
dsp: fix typos
dsp: new files in dsp directory
dsp: more typos
dsp: reworked muxes on rx
dsp: do proper rounding at the end of dsp chain
dsp: add resets for simulation purposes
dsp: tx_dcoffset, not integrated yet
dsp: testbenches for dsp blocks
dsp: reorganized scaling and rounding, removed multipliers (will put back
in a different location)
dsp: use round_sd in small_hb_dec
dsp: increase gain of small_hb_dec because it used to scale down by
factor of 2. Clip if needed.
dsp: no need to keep all the low order bits from the accumulator
dsp: register hb output
dsp: fix off-by-one error in timing of hb_dec
dsp: add guard bit to top of cordic to allow clipping on output instead
of wrapping
dsp: clip in hb_dec to prevent the rare overflow with certain frequencies
at max amplitude
dsp: pass 24 bit wide signals between frontend and dsp core.
u2/u2p: use all 24 bits from the rx_frontend
u1e: update u1e to use new rx_frontend, and give it a 2nd rx dsp core
dsp: do everything at 24 bits wide
dsp: small_hb_dec now 24 bits wide as well
dsp: added tx_frontend, instantiated in u2/u2p
dsp: remove unused setting reg
u1e: new 2 clock fifo, 18 bits by 1K
u1e: new write interface, with 2x clock
dsp: implement iqbal on tx
u1e-dsp: attach tx dc offset and iq balance
u1p: new tx dsp frontend, copied from u1e
u1p: work in dual rx and frontend from u1e
u1e/u1p: new register map for new dsp
Merge branch 'usrp_e100_aux_spi' into dsp_rebase
u1e: experimental rewrite of read path of gpmc
u1e: rearrange gpmc fifo
u1e: the perils of cut and paste
u1e: fix typos
u1p: connect have_packet signal
u1p/u1e: cleanup some warnings, connect the correct clocks
u1e: core compile now works as a fullchip lint
u1p: remove unused ports
u1p: remove uart and bus testing to fit easier
dsp: reset the interpolator when the rate changes, to prevent oscillation
dsp: reduce bitwidth to help timing
N200: detailed map report allows you to see what takes up too much space
removed wb readback of ATR, allowing it to be synthesized as luts
appease the ISE gods
u2/u2p: further qualify the serdes link light
u2p: finish copying over serdes light fix
u2: redo the atr gpio pins, remove some old cruft
atr: forgot to delete this line
u2/u2p: apply atr/gpio changes to u2p
simple_gemac: add parameter to allow disabling rx flow control at compile
time
simple_gemac: remove old 19-bit wide wrapper
u2/u2p: speed up time_64, and remove readbacks on simple_gemac wb regs
dsp: option to remove iq compensation at compile time
dsp: allow tx iq balance to be removed at compile time
vrt: delay the late signal to help with timing
time: register time output to help fpga timing
dsp: clear cic_decim when not enabled
dsp: slow down the time constant of the DC offset correction by a factor
of 16. it may need to be even slower.
b100: gpif_rst resynced to gpif_clk
all: tie unused ram inputs to 1 instead of zero, helps routing
fix typo
all: tie unused ram inputs to 1 instead of zero, helps routing
fix typo
u1e: separate build for E100 and E110, just a different FPGA
u1e: relax GPMC constraints, eases P&R
u1p: proper format in ucf file
u1e,u1p: turn off debug pins, misc cleanups
dsp: ability to set rx dc offset to a fixed value
dsp_engine: new way of doing DSP operations on VITA packets. Example
does 16 to 8 bit conversion
dspengine: insert into the rx chain
dspengine: move the register to VITA_RX_CTRL + 9 instead of + 3 which is
occupied
dsp_engine fix rst -> reset, default to read address
dsp_engine: trailer change to fit standard
dsp_engine: don't use SD rounding in 8 bit mode, so we can have a flat
noise floor.
dsp: new rounding. more complex, but better properties
dsp: make rounding a single bit work again
u2/u2p: remove dead comments and code
u2/u2p: move nearly all setting regs onto dsp_clk
u1e/u1p: remove unused UART
u2/u2p: use new setting_reg based gpios, gets it off of wb
u1p/u1e: partially redone atr and gpio redo
u1e/u1p: removed led setting reg
u1e/u1p: GPIOs switched over to setting regs
b100: remove test features from GPIF to save space
b100: fix warnings, complete removal of test code
u1e: fix unattached nets from copy-paste error
dsp: remove warnings
dsp: remove dsp_buffer and replace with simpler add_routing_header,
dsp: 8 to 16 bit conversion for tx side. believed to be functional
dsp_engine: work with transport header
dsp_rework: more thorough test
dsp_rework: handle longer headers
dsp_rework: testbench enhancements
power_trig: first cut at power trigger with fixed delay
power_trig: test code for power trigger
dsp_engine: fix for upper/lower swap, and odd length packets
Nicholas Corgan (5):
cmake:
Changes images CMakeLists.txt to be consistent with new UHD version
naming system
Changes Windows installer filename to match naming convention of Ubuntu
and Fedora installers
For Windows installers, CMake checks the size of void* to differentiate
between Windows x86 and x64.
Added alternative Docutils install method to UHD docs
Nick Foster (271):
Merge branch 'u2p' of ettus.sourcerepo.com:ettus/fpgapriv into u2p
Merge branch 'u2p' of ettus.sourcerepo.com:ettus/fpgapriv into u2p
Merge branch 'u2p' of ettus.sourcerepo.com:ettus/fpgapriv into u2p
Fixed Makefile.common to correctly generate .mcs files.
Merge branch 'master' of ettus.sourcerepo.com:ettus/uhdpriv into
codec_gains
fixed template problems in gain_group_test
New branch with firmware dir from USRP2P branch.
Firmware compiles.
Deleted manually those files to correspond with USRP2P branch.
Host-side changes to work with the USRP2+.
Merge branch 'codec_gains' of address@hidden:ettus/uhdpriv into usrp2p2
fix timing races on ADC and DAC pins
Merge branch 'u2p' of ettus.sourcerepo.com:ettus/fpgapriv into u2p
Added gain support for USRP2+ ADC.
fixed template problems in gain_group_test
Merge branch 'master' of address@hidden:ettus/uhdpriv into usrp2px
This is a manual merge of codec_gains2 into usrp2py.
Added one more file from codec_gains2...
Interface access methods for users to access dboards.
Ethernet PHY re-do.
Ethernet mods for activity LED.
Merge branch 'usrp2p2' of address@hidden:ettus/uhdpriv into usrp2py
latest bootloader in core, fixed eth_led to be active high, connected eth
clk
Ethernet blinky light changes. Link LED works. D201 (next to PHY) blinks
on TX. Yellow LED on connector blinks on TX/RX.
usrp: gain group should not try to set gain elements if there are none
Added gain range property to rx_codec_get.
Widened SPI slave select bus to 16 bits in host and firmware.
usrp: codec gains, don't bind functio npointers, also add priorities
ADC SPI works. ADC gain interface "works".
ADC gain control works.
Fix for SPI SS > 8 bits wide
use int not rint.
Stripped out all the clock functionality except for init'ing the FPGA.
Clock smarts have been host-side for a while, so this is redundant code.
Added back in clock_mimo_enable stuff since USRP2 breaks without it.
Clock bugs, LED order.
Added DCM reset line to sr.
Merge branch 'master' of address@hidden:ettus/uhdpriv into usrp2p
Interrupt-driven I2C. txrx_uhd uses async i2c for comms.
Bring in changes since last week.
Merge branch 'master' into usrp2p
Merge branch 'master' of address@hidden:ettus/uhdpriv into usrp2p
Branch to make use of quad UART on USRP2P.
Working support for multiple UARTs.
Merge branch 'master' of address@hidden:ettus/uhdpriv into usrp2p
Fixed u2plus_core.v to use quad_uart instead of simple_uart.
Added UART transactions to the DUDE/BRO protocol.
Added host-side support for UART messaging.
Fixed GPS UART stuff. Works OK.
Host-side fixes for GPS UART.
first stab at a GPS driver in gps_ctrl.cpp. not the most expandable thing
in the world but there's only so many GPS interfaces out there.
Added timeout functionality for UART gets() calls. use fngets_timeout().
timeout defined in hal_uart.h.
Increased UART timeout for slow Jackson Labs GPSDO. Fixed up timeout code.
GPS interface works for Jackson Labs devices.
Support for NMEA reads. Uses NMEA parsing instead of Jackson Labs parsing.
Small fix for fngets
Fixed behavior when no GPS present.
Finished GPS driver, more or less.
Brought in changes to SPI to match up with parallel branch so they share
a common protocol.
Fix warnings related to const-ness and volatile-ness.
Removed NACK checking so things don't barf when daughterboards aren't
connected.
first stab at irq'ed spi
syntax
IRQ-based SPI works. Don't try to do multiple transactions without
waiting for results first. In fact, don't try to do
Merge branch 'tx_policy' of ettus.sourcerepo.com:ettus/fpgapriv into
premerge
usrp2: don't forward dbsm errors
Rev firmware compatibility number to 6
UDP firmware update support for USRP2P.
Removed debugging print from usrp2p_fw_update.py
Moved UDP firmware update stuff out of fw_common.h into udp_fw_update.h.
Merge branch 'master' of ettus.sourcerepo.com:ettus/uhdpriv into usrp2p
Merge branch 'usrp2p_udpfw' of ettus.sourcerepo.com:ettus/uhdpriv into
usrp2p
Merge branch 'master' of ettus.sourcerepo.com:ettus/uhdpriv into usrp2p
Merge branch 'master' of ettus.sourcerepo.com:ettus/uhdpriv into usrp2p
Added 12mA current spec to eth phy LED pin.
Ensure ethernet LED pin has 12mA output
Added a sanity checker Python script.
Change to get codec_impl to compile, dur.
Merge branch 'master' of ettus.sourcerepo.com:ettus/uhdpriv into usrp2p
Removing the GPS search stuff until I have time to figure out why the
firmware side keeps timing out.
Fixed PPS. Instantiation was miscapitalized.
EEPROM burning in UHD. Changed some USB device handle stuff. Added
usrp_init_eeprom.cpp. Hacked up the firmware makefile to behave and to generate
.bin EEPROM images instead of IHX.
Merge branch 'usrp1' of ettus.sourcerepo.com:ettus/uhdpriv into usrp1
Added usrp_serial_burner.cpp and capabilities for setting serial number
in mboard_impl. Have not yet added read support.
Added serial number read. Renamed the usrp1-specific utilities.
Removed USRP1 firmware path debug messages
Merge branch 'master' of ettus.sourcerepo.com:ettus/uhdpriv into usrp2p
added db_tvrx, regmap gen_dtt75403_regs.py
TVRX: not done yet but getting there. gain linearization framework in
place.
TVRX: Don't have mboard impl modified for ADC buffer disable. The rest of
TVRX should be in there. Not debugged.
TVRX: First version that works. The gain linearity is still borked.
Merge branch 'master' of ettus.sourcerepo.com:ettus/uhdpriv into tvrx_uhd
TVRX: Fixed spectrum inversion (derp derp derp). Removed debug printing.
TVRX: Mixed up DAC channels. Gain is much more linear now.
Merge branch 'get_codec_rate' of ettus.sourcerepo.com:ettus/uhdpriv into
tvrx_uhd
TVRX: works for USRP and USRP2.
TVRX: Fixed to properly calculate alias frequencies.
Merge branch 'master' of ettus.sourcerepo.com:ettus/uhdpriv into tvrx_uhd
Merge branch 'master' of ettus.sourcerepo.com:ettus/uhdpriv into usrp2p
Made usb_device_handle UHD_API.
TVRX: fixed antenna prop enumeration
UHD: added mutex to fix race condition in device enumeration.
Merge branch 'master' of ettus.sourcerepo.com:ettus/uhdpriv into usrp2p
U2P: 32/64Mbit FLASH support, internal reference support for U2P r2
USRP2P: internal reference selected by default.
U2P: newest bootloader with support for 32Mbit flash
U2P: modified ICAP. turns out ICAP needs clock disabled while CE is not
asserted. which is the point of a CE, but... it works.
U2P: remember your semicolons.
U2P: Bootloader/ICAP updates. 2-stage bootloader works. Uses EEPROM for
state info.
U2P: Whoops.
U2P: Bootloader works, successfully loads production image.
U2P: Working ICAP bootloader. Should be ready for release.
USRP2P: Little bit of commonality in the include files. No functional
change.
Merge branch 'master' of ettus.sourcerepo.com:ettus/uhdpriv into usrp2p
TVRX documentation and a bugfix in the cal table. Named the antenna "RX".
DBSRX: Fixed some ASSERT statements.
UHD: Brought out set_rx_bandwidth for dboards with programmable rx
filters.
UHD: reordered MIMO set_rx_bandwidth arg order
USRP2P: This is surprisingly involved. Adding a consistent interface to
deal with hardware revisions.
USRP2P: mboard rev works through props interface.
Merge branch 'master' of ettus.sourcerepo.com:ettus/uhdpriv into usrp2p
USRP-E: brought loopback test updates in from usrp_e branch.
Merge branch 'master' of ettus.sourcerepo.com:ettus/uhdpriv into usrp2p
Moved mboard rev detection to iface.cpp.
Merge branch 'master' of ettus.sourcerepo.com:ettus/uhdpriv into usrp2p
BasicRX: GPIOs now output 0 to decrease noise pickup.
2+: moved mboard_rev to usrp2/ in preparation for merging upstream
Merge branch 'master' of ettus.sourcerepo.com:ettus/uhdpriv into
usrp2p-next
U2P: Ripped out the mboard_rev_t structure in favor of an enum in
usrp2_regs.hpp and some logic.
U2P: Added U2P stuff to images/ Makefile
U2P: i can't spell
Merge branch 'master' of ettus.sourcerepo.com:ettus/uhdpriv into usrp2p
U2P: saner image burner output messages
while this was legal C++, SWIG hates it
Merge branch 'master' of ettus.sourcerepo.com:ettus/uhdpriv into flow_ctrl
Updated fw rev number in N2XX burner.
Firmware mem map changes for flow ctrl somehow didn't get propagated.
N200 comes up with default IP and MAC when booted in safe mode (button
pushed).
E100: clock sync implemented.
E100: internal ref fix switch statement
u2plus: clock lock pin capitalization fail
packet_router: added set_mimo_clock_delay to clock_ctrl.
ZPU: -ffunction-sections
ZPU: bootloader changes for new ZPU
Merge branch 'zpu' of ettus.sourcerepo.com:ettus/uhdpriv into next
Merge branch 'next' of ettus.sourcerepo.com:ettus/uhdpriv into next
Merge branch 'next' of ettus.sourcerepo.com:ettus/uhdpriv into next
ZPU: bootloader for 210 mods
N210: ZPU firmware bootloader changes
N210: Host memory map changes for ZPU
TVRX: fix bug in rf_gain_to_voltage -- we're hi-side mixing, not lo-side
ZPU: bootloader only checks first 4 bytes of program flash image for
validity
USRP1: Fix ATR for TX/full duplex
USRP1: REALLY fix the full-duplex case.
fu_ranges: dict's keys()/vals() now return non-const to make
BOOST_FOREACH happy on Clang
next: fngets() fixed for GPS driver. polling/timeout moved to host side.
small changes to GPS output text.
next: generalized the GPS interface to any USRP device. just give it a
function to write/read strings to UART.
Merge branch 'next' of ettus.sourcerepo.com:ettus/uhdpriv into next
master: fixed N210 analog ADC gain to "on" to fix RFX noise issue
TVRX: fixed spectrum inversion on USRP1, hopefully for the last $%^&*
time.
TVRX: forgot to disable debug messages
E100: rewrote clkgen-config so it's less incredibly opaque
Merge branch 'clkgen_config' of ettus.sourcerepo.com:ettus/uhdpriv into
usrp_e100_devel
N210: longer GPS timeout, removed try/catch in safe_recv loop (since it
can't throw any more)
Modified the net burner util to perform size and content checks on images.
Modified net burner to allow reading of images from N2XX.
Merge branch 'next' of ettus.sourcerepo.com:ettus/uhdpriv into next
N210: initialize codec gains so it doesn't barf if you call get_rx_gain
before set_rx_gain.
Generalized the mboard_iface into mboard_iface.hpp and made each of the
USRP devices inherit from it.
Generalized mboard_iface and added a SPI convenience class a la I2C
USB zero copy impl: proper cleanup for canceled transfers -- wait for
cancel before freeing
E100: fix test clock output enable
TVRX: no longer muxing in noise on Q channel
N210: Additional checks on both the host and firmware sides of the
firmware updater.
N210: Additional checks on both the host and firmware sides of the
firmware updater.
N210: Created UDP bootloader and modified RMI generation to 16K
N210: UDP bootloader
N210: UDP bootloader first stab (16K boot RAM)
N210: bootram expanded to 16KB (8 BRAMs) and UDP bootloader added
N210: Make new bootloader ignore safe firmware when safe mode button is
pushed.
N210: Moved u2p_init into main app and changed bootloader behavior to not
load safe fw if safe mode button pressed
N210: TXRX_UHD now has bootloader #ifdef'ed into it. Safe firmware now
embedded into FPGA bootloader.
N210: Minor rearranging of bootloader impl in txrx
N210 fw: Move spif_init into bootload_utils
N210: Bootloader includes TXRX. No longer uses safe firmware as backup fw.
N210: implemented mboard sensors for ref lock and MIMO lock
USRP2: Added GPS time support to the sensors interface. gps_time sensor
returns epoch time as time_t. Untested.
USRP2: enable GPS by default
USRP2/N210: firmware UART read no longer drops 20th char
GPS parser fixes for get_time.
E100: fix aux codec ADC reads as per USRP1 in 6f70d1
N210: changes for rev 4 support
N210: how the heck did the PPS fix get dropped again
Merge branch 'master' of ettus.sourcerepo.com:ettus/uhdpriv
UHD: make tx_waveforms MIMO-capable
tx_waveform: no SOB for continuous streaming
tx_timed_samples: fix so EOB isn't set on every pkt
tx_waveforms: don't have to set time_spec for every pkt in the stream
added tx_bursts MIMO burst transmit test
add gain to tx burst app
WBX: keep mixer on when TX idle, and switch TX ant sw to RX when idle to
keep mixer from feeding out when idle.
Merge branch 'master' into burst_test
minor change to tx_bursts
Fixed I2C pin names.
I2C slave address decoding for 16-bit dw instead of 32-bit
select bus is 2 bits wide
u1p: remove extram from Makefile
u1p: added debug0, debug1 for GPIF debugging
B100: added some packet splitter debug pins, removed debug from GPIO
port, swapped I&Q in interleaver
tx_bursts: optional repeat
tx_bursts: minor change
updated sync doc for clarity & examples
N210: added makefiles in for rev 4 versions (use LVDS)
N2XX: this method for defining R3/R4 actually works
B100/USRP1: fix bug where fpga size div by 64 resulted in never finishing
load
N2XX: fix UART bug for GPSDO
N210: stop sending 1 char at a time to the GPSDO
UHD: Orc implementation added and CMake magic put in. Won't link.
UHD: Orc conversion routine works
UHD: Fixed convert_test (scalars backwards), fixed Orc conversions
(endianness backwards).
UHD: added item32<->sc16 conversions in Orc
use temp vars in sc16->item32 to make orcc happy
Remove unnecessary include
NEON detection for E100 in convert/
N2XX: firmware stops device streaming on fw update, and updater script
checks hw rev before proceeding
fw_updater: add support for fictitious "rev 2" N2XX
fw_updater: add broadcast addr finding for *nix/Win
fw_updater: device enumeration support, not integrated into main app yet
fw_updater: decrease discovery timeout, modify win to return bcast
instead of ip
N210 R4 lost fix for ADC data termination
UHD: GPS work.
UHD: implemented gps_locked sensor. usrp2 mboard doesn't init VITA time
if time not valid.
USRP2/N210: set VITA time even if GPS not locked. harmless to do so.
Add GPSDO documentation
Refactor GPS code to duplicate way less stuff, make members private
GPS ctrl fixes for uncooperative Firefly devices (Bastien Auneau)
N2XX: fix bug in firmware updater (don't use local variables for static
data). this fixes the "n210 bricking on update while streaming" bug.
B100/E100: fix ATR RX mode pins not connected
gps_ctrl: make GPSDO parsing more robust, add retries
typo in last commit
save before you commit, thanks
SBX: fix typo in freq range
B100: reset FPGA GPIF fifos correctly so no garbage data on startup
B100: fix order-of-operations issue w/SPI & I2C
B100: don't reset send buffers (screws up TX)
USRP2: don't populate GPS sensors if no GPSDO found. Fixes bug #614.
B100: use gpif_misc on R2 hw, invert direction of gpif_misc pins
B100: LVDS clocking on db outputs
B100: unshadow dboard clock rates so you can set master freq after init
and still tune ok
ZPU/USRP2: first stab at UDP UART firmware
E100: GPSDO serial port level conversion
B100 firmware fix for FPGA load race condition, plus a little cleanup for
readability
B100: modify build_eeprom for correct B100 PID
Init_eeprom: enhancements for B100/reinit of init'ed devices
B100/USRP1: pass in VID/PID from args string so you can specify where to
look for devices if you like
B100: use PA6 for pktend
B100: change B100 PID in usb_descriptors.a51 as well
N210 R4 should be using LVDS TX clock, not CMOS.
Squashed slave mode changes onto master.
B100: moar buffering on TX for better performance in bidirectional
applications
Slave FIFO: fix for PKTEND not asserting @ end of RX.
Fix missing B100 core_compile (poor Git hygeine)
B100 host code changes to remove TX padding, remove RX padding, increase
max allowed rate.
B100 firmware changes to allow slave mode TX/RX.
B100: Modified TX send size to achieve 10.7Msps.
B100/B150: firmware disable FIFOs until host enables to keep junk out
B100: use FPGA external reset on init
B100: External FPGA reset from FX2 reuses fpga_cfg_cclk.
Add Orc functions to convert to sc8. bswap version is a bit of a hack.
B100: Firmware reset tweaks.
B100: enable_gpif(0) disables FIFO output clock on FX2. this prevents the
"stuffing zeroes" problem and improves transport reliability.
tx_bursts: set EOB on nsamps <= spb
Philip Balister (168):
Start renaming stuff in line with product name USRP Embedded.
Start applying order through Makefile.
Merge branch 'u1e_uhd' of address@hidden:ettus/uhd into u1e_uhd
Makefile and usrp-e-spi edits, add i2c test program.
Update read/write test program to new header name and add to Makefile.
Add test program to send characters to the wishbone uart.
Working version.
Minor fixes.
Merge branch 'usrp_e' of address@hidden:ettus/uhd into usrp_e
Spi word length is in bits, not bytes.
Allow variable length spi messages.
Handle 32 bit data to spi controller.
Convert to use register include file. Fix peek/poke16 program.
Don't need to use malloc to get the correct sized struct anymore.
Update to use register definitions from header file.
Yes, I am an idiot.
Add ability to change uart baud rate. (works)
Add program to read from serial port and print to screen. (works)
Attempt to make scripts run inside and outside GHQ.
Test program to verify GPIO on daughterboards. For success, connect gpios
on
Fix typo.
Merge branch 'usrp_e' of address@hidden:ettus/uhd into usrp_e
Add scripts to read and write board id info into usrp e id eeprom
Always put new bin file in /home/root.
usrp-e-i2c always uses hex arguments.
usrp-e-spi: change active edges around.
Initialize data array to help show when reads fail. Report return value
Add program to setup debug pins.
Add register definitions for new transfer scheme.
Update transfer test program to use usrp_transfer_frame struct.
Updates to test programs.
Send only required number of bytes. Do it for longer.
Add program to exercise interface using internal fpga data source and
data sink.
Merge branch 'usrp_e' of address@hidden:ettus/uhdpriv into usrp_e
Various updates to test programs.
Add script to setup board id info in eeprom.
Merge branch 'usrp_e' of address@hidden:ettus/uhdpriv into usrp_e
Update IP address for my home desktop. Change module version to 2.6.33.
Change overrun indication. New progress indicator. Turn on RT scheduler
for
Add a hack to work around a driver race. Remove when teh driver is fixed.
Add hack to work around driver race.
Update path to put module in.
Spi data returned in struct now.
Print an error and exit if open fails for some programs.
First pass at data transfer program that uses CRC.
Update usrp_e.h file from kernel header.
Add program to do initial configuration of the clkgen chip.
Add calculation for data trasnfer rates.
Print a . for every packet received.
Change to 24 bit transfers.
Connect enable to the correct gpio.
Update test program to reflect what is in the FPGA image.
Revert "Update test program to reflect what is in the FPGA image."
Remove rand for now. Fix bug in data rate calculation.
Revert "Revert "Update test program to reflect what is in the FPGA
image.""
Comment out progress indicators.
Keep repo in sync with my churn ...
Rename test program to match FPGA bin file name and add data rate
calculation.
Fix initialization bug.
Use better optimization settings.
Calculate received sample rate for loopback test.
Display data rate in samples/second and fix typo.
Enable realtime scheduling in loopback test to prevent overruns.
Rename loopback test program to match bin file name.
OK, now crc uses the timed interface to set the data rate.
Work on crc testing program. Currently dumps first received packet to the
Divide by 4 to convert byts/sec to samples/sec. Multiply by 4 is right
out.
Update usrp_e.h file. Change programs to use struct element status
instead of flags.
Exit on errors. Run until an error occurs. Alloq for up to 2 sequence
Rename loopback of random length packets test program so we know it needs
Add gitignore file.
Merge branch 'master' of ettus.sourcerepo.com:ettus/uhdpriv into usrp_e
Convert basic test programs to use shorts in the GPP to avoid using
Use largest possible packets for transfers.
Loopback test now supports variable size and works with mmapable ring
buffer.
Merge branch 'usrp_e' of ettus.sourcerepo.com:ettus/uhdpriv into usrp_e
Add usrp-e-mm-loopback to .gitignore.
Convert non-mmaped loopback test program to use new simple read/write api.
Convert to use mmaped rx ring buffer.
Merge branch 'usrp_e' into usrp_e_merge
Merging my work back to usrp_e branch.
Fix to create 90 phase shift on TX.
Really fix TX IQ phase offset.
Build rx_to_file example.
Add program to transmit samples from a file.
Add get setting to the rx_to_file program.
Add gain setting to tx_timed_samples program.
Add gain command line parameter.
Merge branch 'master' of ettus.sourcerepo.com:ettus/uhdpriv into usrp_e
Change clock dividers so DBSRX board locks.
Change TX PGA gain scaling to match gnuradio scaling
Add support for building c programs. Remove -pedantic and -ansi flags.
Move fpga-downloader and usrp-e-loopback into utils so they get packaged
Test if usrp_e kernel module is loaded before trying to load the FPGA. Do
Add usrp-e-debug-pins to utils. This is the wrong place for the regs
header
Add clkgen-config, usrp-e-i2c and usrp-e-spi to the installed utils.
Merge branch 'master' of ettus.sourcerepo.com:ettus/uhdpriv into usrp_e
Convert fc32_to_item32_nswap to use ARM NEON if available.
Restore tx and rx timed smaple programs to the versions in master. They
use floating point.
Allow programs to find usrp_e.h header, even if it is not installed in
/usr/include/linux.
Fix errors.
Merge branch 'usrp_e' of ettus.sourcerepo.com:ettus/uhdpriv into usrp_e
Install main_test so we can test cross compiled uhd.
Reverse I and Q on the wire.
Fix ring buffer size calculation.
Read the ring buffer size from the kernel and use that to set up the
Convert write to use the mmap interface.
Use the ring buffer sizes read from the kernel.
Use a dummy write to start DMA transfers when sending data to the FPGA.
Add more NEON for type conversion.
Add define so uusrp_e support is enabled.
Remove BIT macro
Really enable usrp_e support. Previous commit commented out the ansi flag
Add flag that indicates userspace has started processing a frame.
usrp_e: back out dynamic send/recv samples calculation.
usrp_e: Disable debug.
Merge branch 'master' of ettus.sourcerepo.com:ettus/uhdpriv into
usrp_e_mmap_b2
usrp_e: Do not install main_test anymore.
Merge branch 'usrp_e_mmap_b2' of ettus.sourcerepo.com:ettus/uhdpriv into
usrp_e
usrp-e: Add example that reads data from uhd and sends it over a udp
socket.
Merge branch 'usrp_e' of ettus.sourcerepo.com:ettus/uhdpriv into usrp_e
usrp_e: Add driver compatibility ioctl to header file.
Merge branch 'master' of ettus.sourcerepo.com:ettus/uhdpriv into usrp_e
Merge remote branch 'origin/usrp_e_next' into usrp_e_next
usrp_e: Comment out fpga loading until we unload module during load.
usrp_e : Fix register definitions for COMPAT and others.
usrp_e : Unload the module before loading the FPGA. Reload after the fpga
is loaded.
usrp_eXXX: Only include i2c-dev.h due to struct definition conflicts.
usrp_e : Add missing header file.
usrp e100 : Add i2c header back.
usrp e100 : Add sleep after loading module.
Update timed crc test program to use mmap's interface. Needs testing.
Mark received block as accepted by user space.
Update header from in e100 test programs from main uhd.
Start converting the timed test program to work with mmap interface.
Local changes for wishbone tests, PLease review carefully.
Merge branch 'usrp_e100_devel' of ettus.sourcerepo.com:ettus/uhdpriv into
usrp_e100_devel
Merge branch 'usrp_e100_devel' of ettus.sourcerepo.com:ettus/uhdpriv into
usrp_e100_devel
Fixes for timed fpga interface test program. Still need to solve the CRC
usrp-e100: Check in wip for timed image test program.
Merge branch 'next' of ettus.sourcerepo.com:ettus/uhdpriv into next
usrp-e-crc-rw: Fix data rate calculation.
Fix typo in usage message.
usrp-e-timed test program. Add checks for packet length and sequence
Add back line that mysteriously disappeared. I blame the cat.
Fix endianess for packet length and sequence number for e100 timed image.
usrp-e-mm-loopback : Works with GU fpga image. Cleaned up warnings.
usrp-e-crc-rw : Work with GU fpga image. Cleaned up warnings.
Merge branch 'next' of ettus.sourcerepo.com:ettus/uhdpriv into next
usrp-e-utils : Move loopback and timed test programs into utils
usrp-e-utils : Remove old files.
usrp-e-utils : Delete more old files.
usrp_e : Prevent people from typing in large numbers that crash the
timed tester : Bring out src/dst flags for rx chain for testing.
timed packet generator : Temporarily use a checksum rather than a crc to
validate packet integrity.
usrp_e100: Delete old test scripts.
usrp_e100: Move gpio test program to utils.
usrp_e : Add usrp e1xx gpio test program the usrp e100 utils directory.
usrp_e : Check packet length received from FPGA in case of corruption.
usrp_e : Remove commented out FPGA reset code.
usrp_e1xx : Remove reset offset from register map.
usrp-e-loopback : Fix transfer rate calculation.
usrp-e-timed : Fix stupid typo in tx rate calculation.
Update usrp_e kernel header file copies.
e100 : Adapt kernel header to work in user space.
E1X0 : Remove the spi and i2c test programs.
Try really hard to get cmake to use compiler flags from the toolchain
file.
Add a toolchain file to build cross using e100 toolchain.
Thomas Tsou (45):
usrp1: Add FX2 firmware files
usrp1: Add SPI transaction command to FX2 firmware
usrp1: Add USB transport interfaces
usrp1: Add libusb-1.0 implementations of USB interfaces
usrp1: Add usrp1 implementation
usrp1: Setup dboard interface duality
usrp1: Remove error message for unsupported ATR registers
usrp1: Remove hard coded clock values
Merge branch 'usrp1_next' of ettus.sourcerepo.com:ettus/uhdpriv into
usrp1_next
usrp1: Return unknown (0xff) on invalid I2C read
usrp1: Refactor mboard tuning code
usrp1: Return proper mboard proxy
usrp1: Remove codec gain TODO comments
usrp1: Make underrun/overrun checking rate dependent
usrp1: Change codec transmit gain scaling
usrp1: Fix bug in calculating transmit mux
usrp1: Refactor I/O implementation
usrp1: Remove hard coded value in clock rate property
usrp1: Fix assertion that prevents 32-bit SPI transactions
usrp1: Improve debug output readability
usrp1: Cleanup unnecessary state variables
usrp1: Remove unused overrun/underrun poll variable
usrp1: Modifiy USB interfaces to use new device handle
usrp1: Modifiy USB transport implementations to use new interface
Merge branch 'usrp1_next' into usrp1
Merge branch 'convert_types' into usrp1
usrp1: Fill in missing dboard interface with an empty call
usrp1: Add TODO comments
usrp1: Fix fpga load issue by increasing delay after firmware load
usrp1: Clean up initialization sequence of fpga registers
usrp1: Fix DDC rate storage value and comments for multiple channel
support
usrp1: Only return a list of FSF devices
usrp1: Add missing include for fpga registers
Merge branch 'usrp1_cleanup' into usrp1
usrp1: Disable default codec debug output
usrp1: Disable i2c error messages unless debug is enabled
usrp1: Cleanup libusb device handling
usrp1: Disable default debug output for libusb implementations
usrp1: Handle degenerate managed send buffer cases
usrp1: Wait for USB device renumeration only when necessary
usrp1: Additional comments to libusb transport implementation
usrp1: Remove unused funtions libusb transport
usrp1: Don't flush the stream buffer after every overrun/underrun
usrp1: Read capabilities register
usrp1: Additional comments on libusb transport implemenation
eb (20):
Updated FSF address in all files. Fixes ticket:51
New rbfs. These were compiled using Quartus 6.0 sp1 and include the
post-ADC / pre-DDC digital rssi measurement code.
removed unused/out-of-date bus_interface.v
Applied patch from Brett Trotter that stuffs zeros into the head of the
tx signal processing pipeline when the Tx FIFO is empty.
fixed comment
fixed comment
updated qsf file to Quartus 6.1. No semantic changes
Add new standard configuration for 1 RX w/ half-band, 1 TX
Refactored FPGA *.vh files. Moved common pieces to toplevel/include.
copied usrp_inband_usb from -r4809 features/inband-usb into trunk
New FPGA binaries (.rbfs). These include fixes for the scaling in the
CIC decimator so that signals are now roughly leveled, independent of the
decimation rate. Decimating by 44 now works too ;)
Merged features/inband -r4812:5218 into trunk. This group of changes
includes:
Updated license from GPL version 2 or later to GPL version 3 or later.
Merged features/inband-usb r5224:6306 into trunk. This is
work-in-progress on inband signaling for the USRP1.
Merged r6329:6428 of features/inband-usb + distcheck fixes into trunk.
New rbfs built from r6602 using Quartus II Web Edition version 7.1 SP1
tool version changed
Merged features/inband-usb -r6431:8293 into trunk.
Added firmware support for adc_mux to handle swapping I/Q, etc. Modified
dsp_core_rx.v to swap A and B mapping so that the software thinks that the TVRX
is connected to A/D A.
Built and checked in new rbfs that fix ticket:248 and ticket:290. The
rbfs are built from r11012 and were compiled using Quartus II Version 7.1 build
178 06/25/2007 SP 1 SJ Web Edition.
git repository hosting (2):
Added git ignore files auto created from svn:ignore properties.
Added git ignore files auto created from svn:ignore properties.
ianb (4):
Corrected extfifo code so that all registers that are on SRAM signals are
packed into IOBs
hangedddddddextrnal fifo size to use full NoBL SRAM
Corrected extfifo code so that all registers that are on SRAM signals are
packed into IOBs
hangedddddddextrnal fifo size to use full NoBL SRAM
jcorgan (19):
Houston, we have a trunk.
Partial fix for ticket:81
Adds capability to independently delay the Auto T/R switching signal by a
configurable number of clock ticks, to allow users to precisely align their T/R
output with the pipeline delays in the transmitter.
Merged r5203:5204 from developer branch jcorgan/atr. Fixed ATR delay
enable and reduced delay width to 12 bits.
Merged r5732:5941 from jcorgan/sar into trunk. Adds start of
gr-radar-mono component. Trunk passes distcheck.
Merged r6749:6763 from jcorgan/t179. Fixes ticket:179. New RBFs
synthesized with 7.1SP1.
Merged r6766:6775 from jcorgan/t195. Fixes ticket:195. NOTE: this
removes 8 bit sample width support on receive. Synthesized with 7.1SP1.
Regenerated USRP Makefile.extra
Restores 8-bit sample format support to FPGA code. Synthesized with
7.1SP1.
Merged r9433:9527 from features/gr-usrp2 into trunk. Adds usrp2 and
gr-usrp2 top-level components. Trunk passes distcheck with mb-gcc installed,
but currently not without them. The key issue is that when mb-gcc is not
installed, the build system skips over the usrp2/firmware directory, and the
firmware include files don't get put into the dist tarball. But we can't do
the usual DIST_SUBDIRS method as the firmware is a subpackage.
Merged r9505:9553 from old usrp2/trunk into trunk/usrp2
Merged r10418:10423 from jcorgan/pps into trunk. Adds
usrp2::sync_every_pps
Merged r10504:10528 from michaelld/fix_local_data_install into trunk.
Trunk passes distcheck.
Merged r10712:10765 from jcorgan/gpio into trunk. Adds out-of-band and
streaming GPIO functions for USRP2.
Merged r10770:10887 from jcorgan/iad2 into trunk. Adds alternative USRP2
FPGA build to use integrate-and-dump decimator instead of CIC/HB combination.
This provides a much shorter time duration impulse response for the same
decimation rate, at the expense of worse stop-band rejection.
Fix swapped signals.
Reorganization of debian package directory
Revert erroneous file included in r11424
Add custom FPGA build.
matt (88):
optimized halfband coefficients, courtesy of Larry Doolittle
latest version of quartus
added comments, removed dead code
added comment
allow for varying the bitwidth
removed a parameter
if you ever tried to interpolate by 44 it didn't work. now it does.
proper shifting for the cic decim now keeps signals roughly leveled
registered to meet timing
not used
Allows for changing the interpolation rate dynamically. Stop the
pipeline, set the rate, restart the pipeline. Fixes bug #248.
control CS line on SD card
allow fpga to take over SD card interface
allow fpga to take over sd card interface from cpld
better debug pins
first cut
zbt ram controller
new directory for files
wb_zbt16_b is a quick hack just to be able to safely check the sram. it
is not speed-optimized
attach a 16 bit device to the bus and make it look like a 32 bit device
catch up with latest pin defs of u2_core
added the basic wb<-->extram interface and a serdes interrupt to tell
link status
moved to appropriate places
New serdes status interrupt, clk_status interrupt. New capability to
flush the ICache.
added in mux for DACs
make rev2 compile again
u2_rev2 now works again
hardware control of leds
speed up the diagnostic signals, they were causing timing problems
implemented "reset master clock on next PPS" so we can easily sync
multiple units without MIMO connections
reset the phase when we shut down. Aids in sync
synchronized pps, lots of debug pins changed, works, meets timing
pps sync works, meets timing
24 bit wide z. Can't do this parameterized, unfortunately.
clarify comment
widen cordic on tx side
new cordic
corrected link up detector
detect loss of signal
catching up with shawn. these aren't used here anyway.
trial fix for problem when 3 loads with 1 wait state are followed by a
barrel shift or multiply. Shawn will let us know if this works.
first cut at 64 bit time
work in progress
work in progress
work in progress
support for unmodified dbsrx boards
set all debug stuff to zero
remove support for unmodified dbsrx because there is way too much phase
noise. only modified dbsrx are supported
timing fix, delays the ethernet flow control by a cycle to get it across
the chip. Seems ok in testing.
timing fix. The line address in the buffers still updates now even if
there is an error. Doesn't matter, since the error means the buffer is useless
anyway. This makes meeting timing much easier since the address update does
not depend on the error signal which comes late.
copied over old one which works with icarus
comment out the RMON, which we don't use
optional (but not used) additional buffering in eth rx path.
new fifos copied over from other project
copied over from other project
work in progress on a simpler gigabit-only mac
nearly there
everything but CRC
tx should be fully working now
cleaned up a little
sample packet
we now inhibit our own sending when a received pause frame comes. _rx.v
is currently only a skeleton for testing pause
checkpoint
now checks the crc as well for the received side
variable length delay line, based on srl16
only report result for 1 cycle
address filtering
rx seems to work. haven't test error frames
add fifos to interface to the macs
logic to interface locallink fifos to our mac
added error output line, alternative to simultaneous sof/eof
generate error signal
only write one error into fifo
added a state to ensure the error signal propagates, and now we assert
src_rdy if we have an error to propagate
test multiple error types
Fix for fifo overruns on eth rx in full duplex. Now send re-pause long
before pause is done. Reenabled RMON for the time being
debug ports for fifo level testing. Normally I wouldn't check this in,
but adding these ports actually improves timing. XST strikes again...
simulate a hiccup in the filling of the fifo. If long enough, will cause
a tx underrun.
more thorough tests, including overrun, underrun, crc err, etc.
Properly signals an error and drops the remainder of the packet if there
is an overrun. ERROR_2 changed to ERROR2.
made pause enabling a pin so we can set it
reset synchronizer
copied over from other eth core
first cut at a wishbone interface and wrapping the core
basic wrapper working
now handles odd length packets
from u2p2, autogenerated
mostly formatting and name changes. commented out special purpose pins.
nick (1):
just local commit before updating w/matt's fix
root (14):
Initial checkin of u1e testing code. Some of these may not be really
Initial checkin of useful shell scripts.
Commit wip. Programs that fetch OS code sync now.
Merge branch 'u1e_uhd' of address@hidden:ettus/uhd into u1e_uhd
Commit random test code.
Update usrp1_e.h header file to match kernel driver.
Merge branch 'u1e_uhd' of address@hidden:ettus/uhd into u1e_uhd
Updates for header file change from usrp1_e.h to usrp_e.h.
Remove workaround for driver hang.
Fix really dumb mistake in rad ring buffer code. Add/comment debug
Ignore direction for GPIO 114 since it is always an input.
Ignore direction for GPIO 114 since it is always an input.
Ignore direction for GPIO 114 since it is always an input.
USRP-E: updated the loopback tester for length checking.
trondeau (1):
merge ordm/receiver branch -r5574:5659. Reworks OFDM receiver with
refactored OFDM blocks. A few bug fixes for other blocks have also been slipped
in.
-----------------------------------------------------------------------
hooks/post-receive
--
git://gnuradio.org/jcorgan-uhd
| [Prev in Thread] |
Current Thread |
[Next in Thread] |
- [Commit-gnuradio] git://gnuradio.org/jcorgan-uhd annotated tag, release_003_004_000, created. release_003_004_000,
git version control <=