[Commit-gnuradio] [gnuradio] 103/148: 19-bit fifo handling for receive side of eth/udp system

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nwest pushed a commit to annotated tag old_usrp_devel_udp
in repository gnuradio.

commit 416aa49a226ad13e4580879b39586c77beda8098
Author: Matt Ettus <address@hidden>
Date:   Thu Sep 10 22:52:08 2009 -0700

    19-bit fifo handling for receive side of eth/udp system
---
 usrp2/fpga/control_lib/newfifo/fifo19_rxrealign.v | 42 +++++++++++
 usrp2/fpga/control_lib/newfifo/ll8_to_fifo19.v    | 86 +++++++++++------------
 2 files changed, 83 insertions(+), 45 deletions(-)

diff --git a/usrp2/fpga/control_lib/newfifo/fifo19_rxrealign.v 
b/usrp2/fpga/control_lib/newfifo/fifo19_rxrealign.v
new file mode 100644
index 0000000..35ad909
--- /dev/null
+++ b/usrp2/fpga/control_lib/newfifo/fifo19_rxrealign.v
@@ -0,0 +1,42 @@
+
+
+//  Adds a junk line at the beginning of every packet, which the
+//   following stages should ignore.  This gives us proper alignment due
+//   to the 14 byte ethernet header
+
+// Bit 18 -- odd length
+// Bit 17 -- eof
+// Bit 16 -- sof
+// Bit 15:0 -- data
+
+module fifo19_rxrealign
+  (input clk, input reset, input clear,
+   input [18:0] datain, input src_rdy_i, output dst_rdy_o,
+   output [18:0] dataout, output src_rdy_o, input dst_rdy_i);
+   
+   reg         rxre_state;
+   localparam RXRE_DUMMY  = 0;
+   localparam RXRE_PKT           = 1;
+   
+   assign dataout[18]    = datain[18];
+   assign dataout[17]    = datain[17];
+   assign dataout[16]    = (rxre_state==RXRE_DUMMY) | (datain[17] & 
datain[16]);  // allows for passing error signal
+   assign dataout[15:0] = datain[15:0];
+   
+   always @(posedge clk)
+     if(reset | clear)
+       rxre_state <= RXRE_DUMMY;
+     else if(src_rdy_i & dst_rdy_i)
+       case(rxre_state)
+        RXRE_DUMMY :
+          rxre_state <= RXRE_PKT;
+        RXRE_PKT :
+          if(datain[17])   // if eof or error
+            rxre_state <= RXRE_DUMMY;
+       endcase // case (rxre_state)
+
+   assign src_rdy_o     = src_rdy_i & dst_rdy_i;   // Send anytime both sides 
are ready
+   assign dst_rdy_o = src_rdy_i & dst_rdy_i & (rxre_state == RXRE_PKT);  // 
Only consume after the dummy
+   
+endmodule // fifo19_rxrealign
+
diff --git a/usrp2/fpga/control_lib/newfifo/ll8_to_fifo19.v 
b/usrp2/fpga/control_lib/newfifo/ll8_to_fifo19.v
index c65be51..af3b91a 100644
--- a/usrp2/fpga/control_lib/newfifo/ll8_to_fifo19.v
+++ b/usrp2/fpga/control_lib/newfifo/ll8_to_fifo19.v
@@ -10,68 +10,64 @@ module ll8_to_fifo19
    output [18:0] f19_data,
    output f19_src_rdy_o,
    input f19_dst_rdy_i );
-
+   
+   localparam XFER_EMPTY       = 0;
+   localparam XFER_HALF        = 1;
+   localparam XFER_HALF_WRITE  = 3;
+   
    // Why anybody would use active low in an FPGA is beyond me...
    wire  ll_sof      = ~ll_sof_n;
    wire  ll_eof      = ~ll_eof_n;
    wire  ll_src_rdy  = ~ll_src_rdy_n;
    wire  ll_dst_rdy;
    assign    ll_dst_rdy_n  = ~ll_dst_rdy;
-
-   wire xfer_out          = f19_src_rdy_o & f19_dst_rdy_i;
-   //  wire xfer_in       = ll_src_rdy & ll_dst_rdy;   Not needed
    
-   reg          f19_sof, f19_eof, f19_occ;
+   wire  xfer_out         = f19_src_rdy_o & f19_dst_rdy_i;
+   wire  xfer_in          = ll_src_rdy & ll_dst_rdy; 
+   
+   reg          hold_sof;
+   wire  f19_sof, f19_eof, f19_occ;
    
    reg [1:0] state;
-   reg [7:0] dat0, dat1;
-
-   always @(posedge clk)
-     if(ll_src_rdy & ((state==0)|xfer_out))
-       f19_sof <= ll_sof;
-
+   reg [7:0] hold_reg;
+   
    always @(posedge clk)
-     if(ll_src_rdy & ((state != 2)|xfer_out))
-       f19_eof <= ll_eof;
-
+     if(ll_src_rdy & (state==XFER_EMPTY))
+       hold_reg              <= ll_data;
+   
    always @(posedge clk)
-     if(ll_eof)
-       f19_occ <= ~state[0];
-     else
-       f19_occ <= 0;
+     if(ll_sof & (state==XFER_EMPTY))
+       hold_sof              <= 1;
+     else if(xfer_out)
+       hold_sof              <= 0;
    
    always @(posedge clk)
-     if(reset)
-       state   <= 0;
+     if(reset | clear)
+       state                 <= XFER_EMPTY;
      else
-       if(ll_src_rdy)
-        case(state)
-          0 : 
+       case(state)
+        XFER_EMPTY :
+          if(ll_src_rdy)
             if(ll_eof)
-              state <= 2;
+              state          <= XFER_HALF_WRITE;
             else
-              state <= 1;
-          1 : 
-            state <= 2;
-          2 : 
-            if(xfer_out)
-              state       <= 1;
-        endcase // case(state)
-       else
-        if(xfer_out)
-          state           <= 0;
-
-   always @(posedge clk)
-     if(ll_src_rdy & (state==1))
-       dat1               <= ll_data;
-
-   always @(posedge clk)
-     if(ll_src_rdy & ((state==0) | xfer_out))
-       dat0               <= ll_data;
+              state          <= XFER_HALF;
+        XFER_HALF :
+          if(ll_src_rdy & f19_dst_rdy_i)
+              state          <= XFER_EMPTY;
+         XFER_HALF_WRITE :
+          if(f19_dst_rdy_i)
+            state      <= XFER_EMPTY;
+       endcase // case (state)
+      
+   assign ll_dst_rdy    = (state==XFER_EMPTY) | 
((state==XFER_HALF)&f19_dst_rdy_i);
+   assign f19_src_rdy_o  = (state==XFER_HALF_WRITE) | 
((state==XFER_HALF)&ll_src_rdy);
+   
+   assign f19_sof       = hold_sof | (ll_sof & (state==XFER_HALF));
+   assign f19_eof       = (state == XFER_HALF_WRITE) | ll_eof;
+   assign f19_occ       = (state == XFER_HALF_WRITE);
    
-   assign    ll_dst_rdy     = xfer_out | (state != 2);
-   assign    f19_data      = {f19_occ,f19_eof,f19_sof,dat0,dat1};
-   assign    f19_src_rdy_o  = (state == 2);
+   assign f19_data      = {f19_occ,f19_eof,f19_sof,hold_reg,ll_data};
       
 endmodule // ll8_to_fifo19