****library: "xmit" version: 6.03 aids: 14 aidname: user aidname: io aidname: compaction aidname: pla aidname: routing aidname: silicon-compiler aidname: vhdl-compiler aidname: compensation aidname: logeffort aidname: network aidname: drc aidname: erc aidname: simulation aidname: project userbits: 70 techcount: 16 techname: generic lambda: 2000 techname: nmos lambda: 4000 techname: cmos lambda: 4000 techname: mocmos lambda: 400 variables: 1 TECH_last_state[01,00]: 8 techname: mocmosold lambda: 2000 techname: mocmossub lambda: 400 variables: 1 TECH_last_state[01,00]: 8 techname: bicmos lambda: 2000 techname: rcmos lambda: 2000 techname: cmosdodn lambda: 2000 techname: bipolar lambda: 4000 techname: schematic lambda: 4000 techname: fpga lambda: 2000 techname: pcb lambda: 2540000 techname: artwork lambda: 4000 variables: 1 TECH_last_state[01,00]: 0 techname: gem lambda: 2000 techname: efido lambda: 20000 view: schematic-page-1{p1} view: layout{lay} view: schematic{sch} view: icon{ic} view: documentation{doc} view: compensated{comp} view: skeleton{sk} view: Verilog{ver} view: VHDL{vhdl} view: netlist{net} view: netlist-als-format{net-als} view: netlist-quisc-format{net-quisc} view: netlist-silos-format{net-silos} view: netlist-rsim-format{net-rsim} view: netlist-netlisp-format{net-netlisp} view: simulation-snapshot{sim} view: unknown{} cellcount: 2 maincell: 0 ***cell: 0 name: uusi{sch} version: 1 creationdate: 991675498 revisiondate: 991676548 lowx: -40000 highx: 4000 lowy: -20000 highy: 28000 aadirty: 6638 userbits: 0 nodes: 8 arcs: 8 porttypes: 4 variables: 1 SIM_window_signal_order[04204,00]: ["A","B","C","D"] **node: 0 type: schematic:Wire_Pin lowx: -10000 highx: -6000 lowy: 2000 highy: 6000 rotation: 0 transpose: 0 userbits: 68608 *port: wire arc: 0 arc: 1 arc: 2 **node: 1 type: schematic:Wire_Pin lowx: 2000 highx: 6000 lowy: 2000 highy: 6000 rotation: 0 transpose: 0 userbits: 68608 variables: 1 NODE_name[04,00]: "node7" *port: wire arc: 0 exported: 3 **node: 2 type: schematic:Wire_Pin lowx: -18000 highx: -14000 lowy: -22000 highy: -18000 rotation: 0 transpose: 0 userbits: 3072 variables: 1 NODE_name[04,00]: "node1" *port: wire arc: 3 exported: 0 **node: 3 type: schematic:Wire_Pin lowx: -18000 highx: -14000 lowy: 26000 highy: 30000 rotation: 0 transpose: 0 userbits: 3072 variables: 1 NODE_name[04,00]: "node2" *port: wire arc: 4 exported: 1 **node: 4 type: schematic:Wire_Pin lowx: -26000 highx: -22000 lowy: 2000 highy: 6000 rotation: 0 transpose: 0 userbits: 3072 *port: wire arc: 5 arc: 6 arc: 7 **node: 5 type: schematic:Wire_Pin lowx: -42000 highx: -38000 lowy: 2000 highy: 6000 rotation: 0 transpose: 0 userbits: 3072 variables: 1 NODE_name[04,00]: "node4" *port: wire arc: 5 exported: 2 **node: 6 type: schematic:Transistor lowx: -24000 highx: -8000 lowy: -20000 highy: -4000 rotation: 1800 transpose: 0 userbits: 68608 variables: 2 NODE_name[04,00]: "node5" SCHEM_transistor_type[0104,020100001200]: "2/2" *port: g arc: 3 *port: s arc: 2 *port: d arc: 6 **node: 7 type: schematic:Transistor lowx: -24000 highx: -8000 lowy: 12000 highy: 28000 rotation: 0 transpose: 0 userbits: 330752 variables: 2 NODE_name[04,00]: "node6" SCHEM_transistor_type[0104,020100001200]: "2/2" *port: g arc: 4 *port: s arc: 7 *port: d arc: 1 **porttype: 0 subnode: 2 subport: wire name: a descript: 704 userbits: 92160 **porttype: 1 subnode: 3 subport: wire name: b descript: 704 userbits: 92160 **porttype: 2 subnode: 5 subport: wire name: c descript: 704 userbits: 92160 **porttype: 3 subnode: 1 subport: wire name: d descript: 704 userbits: 92160 **arc: 0 type: schematic:wire width: 0 length: 12000 userbits: 813694982 *end: 0 node: 0 nodeport: wire xpos: -8000 ypos: 4000 *end: 1 node: 1 nodeport: wire xpos: 4000 ypos: 4000 **arc: 1 type: schematic:wire width: 0 length: 8000 userbits: 813697862 *end: 0 node: 0 nodeport: wire xpos: -8000 ypos: 4000 *end: 1 node: 7 nodeport: d xpos: -8000 ypos: 12000 **arc: 2 type: schematic:wire width: 0 length: 8000 userbits: 813697862 *end: 0 node: 6 nodeport: s xpos: -8000 ypos: -4000 *end: 1 node: 0 nodeport: wire xpos: -8000 ypos: 4000 **arc: 3 type: schematic:wire width: 0 length: 4000 userbits: 813703618 *end: 0 node: 6 nodeport: g xpos: -16000 ypos: -16000 *end: 1 node: 2 nodeport: wire xpos: -16000 ypos: -20000 **arc: 4 type: schematic:wire width: 0 length: 4000 userbits: 830475074 *end: 0 node: 7 nodeport: g xpos: -16000 ypos: 24000 *end: 1 node: 3 nodeport: wire xpos: -16000 ypos: 28000 **arc: 5 type: schematic:wire width: 0 length: 16000 userbits: 813694978 *end: 0 node: 5 nodeport: wire xpos: -40000 ypos: 4000 *end: 1 node: 4 nodeport: wire xpos: -24000 ypos: 4000 **arc: 6 type: schematic:wire width: 0 length: 8000 userbits: 813703618 *end: 0 node: 4 nodeport: wire xpos: -24000 ypos: 4000 *end: 1 node: 6 nodeport: d xpos: -24000 ypos: -4000 **arc: 7 type: schematic:wire width: 0 length: 8000 userbits: 813703618 *end: 0 node: 7 nodeport: s xpos: -24000 ypos: 12000 *end: 1 node: 4 nodeport: wire xpos: -24000 ypos: 4000 celldone: uusi ***cell: 1 name: uusi{doc} version: 1 creationdate: 991675922 revisiondate: 991676725 lowx: 0 highx: 0 lowy: 0 highy: 0 aadirty: 2542 userbits: 0 nodes: 0 arcs: 0 porttypes: 0 variables: 1 FACET_message[022204,00]: ["This component should be a transmission gate.","When a=1 and b=0 it's ON.","","Let's try that in the simulator. Start simulator","and enable transmission gate (set a=1 and b=0","in the beginning of timeline).","","Then move the simulator cursor 100ns or so forward.","Set c=1 (or 0). d changes appropriately to the same","value. Good. Move the cursor still a bit more forward,","something like 50ns and set c=0 (or 1).","","d should change along with c to the same state","but instead the simulator display just lots of white and purple.","A short-circuit? It shouldn't.","","This is electric 6.03.",""] celldone: uusi