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RE: [Discuss-gnuradio] Reducing the ADC sample rate
From: |
Robitaille, Michael |
Subject: |
RE: [Discuss-gnuradio] Reducing the ADC sample rate |
Date: |
Tue, 15 Nov 2005 11:24:49 -0700 |
Oops, I posted without a subject
This is an attempt at correcting it.
Will look at your reply n4hy.
Thanks,
Mike
-----Original Message-----
From: n4hy [mailto:address@hidden
Sent: Tuesday, November 15, 2005 9:18 AM
To: Robitaille, Michael
Cc: address@hidden
Subject: Re: [Discuss-gnuradio] (no subject)
Here is <A> way to accomplish your goal:
You need to have your final sample rate be N samples per second. I will
assume you want (-N/2,N/2) complex frequency.
Choose a decimation ratio in the FPGA such that the Nyquist for the
decimated frequency is LARGER than or equal to N/2. Let this sample
rate be M complex samples per second coming across the USB.
If it is M=N, you are done. If not, then we have more work to do. You
would use the rational or fractional resampler code block to do IN
SOFTWARE the rate change from M to N. (N could be fractional and then
you would use fractional interpolator or resampler).
The use of the halfbands is preferred to the cascaded integrator combs
(CIC) because of the flatness of the response and better group delay
characteristics near the "cutoff".
I guess the point is, if you want a sample rate that is less than the
high speed A/D, you can get it with the existing processing system
(within reason and the ability of your computer to take in data from
USB). That is the reason for our questions, we are not implying that
you don't know signal processing but we are GUESSING that you didn't
know you could all of this with the system as it is now.
Is this clearer on what it is you would do? It would be instructive I
am sure for you to hook together the processing elements in a flow graph
using python to see how the code is assembled.
Bob
Robitaille, Michael wrote:
>
>
> On Monday, November 14, 2005 5:59 PM McGwier
> [mailto:address@hidden wrote:
>
>
>
>> I am attempting to understand what advantage you would gain by reducing
>
>> the sample rate. The FPGA's only jobs are run an oscillator, mix, and
>
>> resample using special form filters. Now that the halfband filters are
>
>> in, you can reduce the sample rate and get a very nice response in so
>
>> doing. You could then proceed to operate on the downsampled signal in
>
>> the computer. I just don't under the system problem you are attempting
>
>> to solve by changing the hardware in this case. Could you elaborate?
>
>
>
>
>
>
>
> Could you provide an example of how to use the halfband filters for
> downsampling?
>
>
>
>
>
> PS: See my other response for an explanation on why change the sample
> rate. I am not sure if performing decimation does the same effect for
> moving under sampled images in the FFT frequency response.
>
>
>
> Thanks,
>
> Mike
>
>
>
>------------------------------------------------------------------------
>
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>
- [Discuss-gnuradio] Reducing the ADC sample rate, address@hidden, 2005/11/11
- RE: [Discuss-gnuradio] Reducing the ADC sample rate, Robitaille, Michael, 2005/11/15
- RE: [Discuss-gnuradio] Reducing the ADC sample rate, Robitaille, Michael, 2005/11/15
- RE: [Discuss-gnuradio] Reducing the ADC sample rate,
Robitaille, Michael <=
- RE: [Discuss-gnuradio] Reducing the ADC sample rate, address@hidden, 2005/11/15