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Re: [Discuss-gnuradio] USB Issues
From: |
Eric Blossom |
Subject: |
Re: [Discuss-gnuradio] USB Issues |
Date: |
Tue, 17 Jan 2006 16:33:33 -0800 |
User-agent: |
Mutt/1.5.6i |
On Tue, Jan 17, 2006 at 06:10:43PM -0500, Brian Dunn wrote:
> Hi Eric -
>
> I've taken a guess at what needs to be done to look at the RD and WR
> signals needed for USB debugging. If I'm way off, could you point me
> in the right direction? The two main questions I have are
> 1) What do we give u._write_oe(...)? I'm guessing your "be careful"
> was referring to making sure we don't enable outputs that are
> connected to another IC as outputs, PWR, or GND.
"be careful" just means be sure you've got basic tx and rx boards
connected.
u._write_oe(0, 0xffff, 0xffff)
> 2) How does the verilog (.v) get compiled? Do we need a separate
> utility to do this or does rebuilding /usrp do this automatically?
We use the free (beer) Quartus II Web Edition tools available at
www.altera.com. They only run under Windows. If this is a pain, just
say so and I'll build the FPGA image for you.
> Here's my attempt:
>
> In /usrp/firmware/include/fpga_regs_common.v change
> `define FR_DEBUG_EN 7'd14
> to
> `define FR_DEBUG_EN 7'd15
> so that all 4 daughter cards i/o pins are controlled by the FPGA.
> (7'd15 = b0001111)
Not quite. The FR_* defines are the register number definitions.
Don't change anything there. We just set the register value from python:
from usrp_fpga_regs import *
u._write_fpga_reg(FR_DEBUG_EN, 0x0003) # enable debug output on TX_A, RX_A
> In /usrp/fpga/toplevel/usrp_std/usrp_std.v change
> .debug_0(rx_debugbus),.debug_1(ddc0_in_i),
> to
> .debug_0(rx_debugbus),.debug_1(tx_debugbus),
> so that tx_debug (contains WR) is also available on a daughter card.
> Assuming (?): >>> Yes, this is correct
> .debug0 -> TX_A
> .debug1 -> RX_A
> .debug2 -> TX_B
> .debug3 -> RX_B,
>
> TX_A header will be rx_debugbus defined in rx_buffer.v as:
> assign debugbus[0] = RD;
> assign debugbus[1] = rx_overrun;
> assign debugbus[2] = read_count[8];
> assign debugbus[3] = rx_full;
> assign debugbus[4] = rxstrobe;
> assign debugbus[5] = usbclk;
> assign debugbus[6] = have_pkt_rdy;
> assign debugbus[10:7] = store_next;
> assign debugbus[15:11] = bitwidth;
>
> RX_A header will be tx_debugbus defined in tx_buffer.v as:
> assign debugbus[0] = WR;
> assign debugbus[1] = have_space;
> assign debugbus[2] = tx_empty;
> assign debugbus[3] = tx_full;
> assign debugbus[4] = tx_underrun;
> assign debugbus[5] = write_count[8];
> assign debugbus[6] = txstrobe;
> assign debugbus[7] = rdreq;
> assign debugbus[11:8] = load_next;
>
> In benchmark_usb.py enable the outputs by adding
> u._write_oe(...)
Yep. You'll need:
from usrp_fpga_regs import *
usrp_rx._write_fpga_reg(FR_DEBUG_EN, 0x0003) # enable debug output on TX_A,
RX_A
usrp_rx._write_oe(0, 0xffff, 0xffff) # make all pins output from FPGA
usrp_tx._write_oe(0, 0xffff, 0xffff)
> Compile the verilog?
Fire up Quartus then "File / Open Project". The file you're looking
for is in usrp/fpga/toplevel/usrp_std
Once the project is open, press the button on the button bar that looks
like the tape recorder "Play" symbol (the right-facing triangle).
Wait 20 minutes. Enjoy.
Copy output file usrp_std.rbf to <prefix>/share/usrp/rev2/usrp_fpga.rbf
> Rebuild /usrp and then run modified benchmark_usb.py
Shouldn't have to rebuild usrp. Just rerun the benchmark.
> Thanks,
> Brian
Eric
- [Discuss-gnuradio] USB Issues, Michael Dickens, 2006/01/09
- [Discuss-gnuradio] USB Issues, Michael Dickens, 2006/01/14
- Re: [Discuss-gnuradio] USB Issues, Eric Blossom, 2006/01/14
- Re: [Discuss-gnuradio] USB Issues, Michael Dickens, 2006/01/15
- Re: [Discuss-gnuradio] USB Issues, Michael Dickens, 2006/01/17
- Re: [Discuss-gnuradio] USB Issues, Eric Blossom, 2006/01/17
- Message not available
- Re: [Discuss-gnuradio] USB Issues,
Eric Blossom <=
- Re: [Discuss-gnuradio] USB Issues, Brian Dunn, 2006/01/19
- Re: [Discuss-gnuradio] USB Issues, Eric Blossom, 2006/01/19