Re: [Discuss-gnuradio] Daughter board pins

Hi Oussama.

Thanks for this. It's exactly what I needed :) Unfortunately I cannot test it out just yet. In probing with my oscilloscope, I blew the small fuse on the board and now have to wait for our support services to fix it. :(

I'll let you know if it works out for me when I get my board back.

Thanks again. Much appreciated.

You're welcome. Let me know how it goes.

Andrew

Good luck.

Oussama.

----- Original Message -----

From: Oussama Sekkat

To: Andrew Borg

Sent: Wednesday, September 20, 2006 10:27 PM

Subject: Re: [Discuss-gnuradio] Daughter board pins

Hi Andrew,

Eric Blossom showed me how to enable those pins and use them.

It turns out, you can control those pins either form the host or from the FPGA.

From the host, using python, you can enable the output pins you want to use and write whatever value you want to them.
Here are the functions that do that: (copy from gr-usrp/src/usrp1.i)

/*!
* \brief Write direction register (output enables) for pins that go to daughterboard.
*
* \param which_dboard [0,1] which d'board
* \param value value to write into register
* \param mask which bits of value to write into reg
*
* Each d'board has 16-bits of general purpose i/o.
* Setting the bit makes it an output from the FPGA to the d'board.
*
* This register is initialized based on a value stored in the
* d'board EEPROM. In general, you shouldn't be using this routine
* without a very good reason. Using this method incorrectly will
* kill your USRP motherboard and/or daughterboard.
*/
bool _write_oe (int which_dboard, int value, int mask);

/*!
* \brief Write daughterboard i/o pin value
*
* \param which_dboard [0,1] which d'board
* \param value value to write into register
* \param mask which bits of value to write into reg
*/
bool write_io (int which_dboard, int value, int mask);

/*!
* \brief Read daughterboard i/o pin value
*
* \param which_dboard [0,1] which d'board
* \returns register value if successful, else READ_FAILED
*/
int read_io (int which_dboard);

Here is a sample code that I got from Eric:

# Assumes Basic_Tx in slot A.
# Do not do this blindly! Output enabing all the i/o pins
# on other daughterboards will cause problems (burn up daughterboard
# and/or FPGA)

u = usrp.sink_c(0, 64)

side = 0 # side A
u._write_oe(side, 0xffff, 0xffff) # set all i/o pins as outputs
counter = 0
while 1:
u.write_io(side, counter, 0xffff)
counter = (counter + 1) & 0xffff

As you see, this will implement a counter on the 16 output pins of daugtherboard A.

In order to control the pins from the FPGA, you need to output enable them and enable them as DEBUG pins from the host . u enable them as debug output by writing to the
FR_DEBUG_ENABLE register in the FPGA.

from usrp/firmware/include/fpga_regs_common.h:

// If the corresponding bit is set, internal FPGA debug circuitry
// controls the i/o pins for the associated bank of daughterboard
// i/o pins. Typically used for debugging FPGA designs.

#define FR_DEBUG_EN 14
# define bmFR_DEBUG_EN_TX_A (1 << 0) // debug controls TX_A i/o
# define bmFR_DEBUG_EN_RX_A (1 << 1) // debug controls RX_A i/o
# define bmFR_DEBUG_EN_TX_B (1 << 2) // debug controls TX_B i/o
# define bmFR_DEBUG_EN_RX_B (1 << 3) // debug controls RX_B i/o

Here is an example on how to write to those register from python:

from usrp_fpga_regs import *

u = usrp.sink_c(0, 64)
u._write_oe(0, 0xffff, 0xffff)
u._write_fpga_reg(FR_DEBUG_EN, bmFR_DEBUG_EN_TX_A)

Now, if you look at the verilog code , the usrp_std.v module instantiates the master_control.v module.
from: usrp/fpga/toplevel/usrp_std/usrp_std.v:

wire [15:0] reg_0,reg_1,reg_2,reg_3;
master_control master_control
( .master_clk(clk64),.usbclk(usbclk),
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
.tx_bus_reset(tx_bus_reset),.rx_bus_reset(rx_bus_reset),
.tx_dsp_reset(tx_dsp_reset),.rx_dsp_reset(rx_dsp_reset),
.enable_tx(enable_tx),.enable_rx(enable_rx),
.interp_rate(interp_rate),.decim_rate(decim_rate),
.tx_sample_strobe(tx_sample_strobe),.strobe_interp(strobe_interp),
.rx_sample_strobe(rx_sample_strobe),.strobe_decim(strobe_decim),
.tx_empty(tx_empty),
//.debug_0(rx_a_a),.debug_1(ddc0_in_i),
.debug_0(rx_debugbus),.debug_1(ddc0_in_i),
.debug_2({rx_sample_strobe,strobe_decim,serial_strobe,serial_addr}),.debug_3({rx_dsp_reset,tx_dsp_reset,rx_bus_reset,tx_bus_reset,enable_rx,tx_underrun,rx_overrun,decim_rate}),
.reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3) );

the inputs debug_0, debug_1....debug_3 will be the signals that get sent to the pins in daughterboard TX_A. RX_A, TX_B, RX_B (respectively)

You can then send any signal you want to any of the debug pins, recompile the verilog code and load that to the board.

Good luck,

Oussama.

On 9/20/06, Andrew Borg <address@hidden> wrote:

Hi. I'm trying to do some FPGA development on the USRP and would like some information if anyone has it readily available.

I'd like to capture the output from the board (same data that goes to the USB) from a daughterboard. I understand that I can do this by using the pins on the BasicRX board. However, my oscilloscope did not pick up any signals. Is there somewhere I need to tinker to get the output on these pins? I'm tempted to do a dirty Verliog hack but I feel there must be a clean way of doing this somewhere.

Thanks

Andrew

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From:	Andrew Borg
Subject:	Re: [Discuss-gnuradio] Daughter board pins
Date:	Tue, 26 Sep 2006 15:15:16 +0100