Re: [Discuss-gnuradio] Running a Test Simulation of FPGA Code withQuartus

[Jeff Brower]

Reid-

> I've written a small Verilog module for the FPGA on the USRP to do phase
> recovery.  I'd like to test it in isolation before I try it out on the board,
> but I'm having major problems feeding Quartus two 16 bit sine and cosine
> signals with a random phase offset.  The idea is that q_out after the phase
> locked loop should be zero for this case, and noise for a real signal.  It
> seems that the only tools for generating signals within Quartus basically let
> you manually specify integer levels for bit vectors and a bunch of other 
> things
> for single bit wires.  The alternative to using their powerless signal
> generation system is to import some waveform files, the formats of which can 
> be
> vwf/cvwf, vec, tbl, scf, and vcd.  Vcd and vwf/cvwf are Quartus specific and 
> the
> others are mostly compatibility layers with Max+Plus and such.  Does anyone 
> know
> of a tool that can generate sine waves and export waveforms in these formats?
> Or do people just burn their Verilog code to the board to test it?

I'm not sure of the lookup table (LUT) capability of the Cyclone I, or how much 
LUT
capacity remains in the standard USRP build...but my suggestion would be to use 
LUTs
for cosine and sine data.  You could make one table, and use an offset to 
determine
sine vs. cosine and also adjust phase.

One advantage to this approach is that your simulation method would be the same 
as in
actual logic.  Plus you don't have to mess around with importing .wav or other 
data
files into the simulator, which I've never found straightforward and reliable.

-Jeff