[Discuss-gnuradio] Bus widths and data rates

[TomasOMaille]

Hello,

I have been trying to understand the tx and rx data paths through the AD9862
and the FPGA (standard configuration).

RX side:

 - The two ADCs of the AD9862 push data onto two 12 bit buses

 - After the FPGA MUX the 16 bit I/Q signals pass into the assigned DDC

 - Are four extra bits assigned to the received I/Q when they arrive onto
the FPGA?

TX side:

 - The 16 bit I/Q signals pass into the FPGA demux and arrive at the
appropriate AD9862 chip

 - I/Q signals arrive interleaved on a 14 bit bus into the AD9862 

 - Are the I/Q signals truncated by 2 bits before they are sent onto the 14
bit bus?

Thanks,

Tomas
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