[Discuss-gnuradio] Algorithm RSSI on FPGA

[tarara]

Hi,
I'm working on RSSI value and reading mailing lists I have understood how RSSI
is calculated. In the algorithm of RSSI in verilog alpha value is 2^-10 because
the shift is made on 10 bits. I want to change alpha value (decrease or
increase) but I don't understand how I can change it in the algorithm in
verilog. Could you help me?

Thank you very much.