Re: [Discuss-gnuradio] USRP synchronization

[ValentinG]

Thanks a lot for the answers!

Yes all of our boards are USRP2s.

We do have a common PPS signal provided by the external signal generator. We
use code from the VRT branch and call set_time_at_next_pps for all 4 boards
to reset their times. Then we call start streaming for all 4 boards some
seconds later. This as we understand ensures the alignment of the samples
received.

We use RFX2400 daughterboards.

There are a few other questions we wanted to ask:

1.) We observe a phase shift between MB clocks on different USRP2
MotherBoards which changes each time the USRP2 is reset. Is there a finite
number of possibilities for that phase difference due to its PLL? How many
are there?
2.) Does the PLL on the daughterboards uses the clock, generated on the MBs
as a reference to lock the VCO signal used for downconversion? Or does it
use the external 10MHz clock as the reference?
3.) If there is a finite number for the phase differences (N) between MB
clocks and these are used to produce the down-converter signal, which can
also have a finite number of phase differences (M), this would imply that we
can have NxM different phases, correct?

4.) Do the PLL's on the daugherboard tune every time a C++ or Python program
is run or every time the board is powered on? i.e. for phased arrays will we
just need to calibrate every time the board is powered on or every time we
take a given stream of data?
5.) How can we change the number of possible phases for the daughterboard?
6.) Does reducing this number increase lock time?
7.) How can we tune so there is no ambiguity in the phase of the boards like
you suggested?

Thanks,
Valentin




Matt Ettus wrote:
> 
> On 03/09/2010 09:20 AM, ValentinG wrote:
>>
>> Hi All,
>>
>> We are trying to use 4 USRPs to extract the phase information due to
>> differences in positions of the antennas.
>>
>> In a standard communications system an internally generated carrier is
>> locked IN PHASE with the incoming signal to perform downconversion (see
>> Figure 1.).
>> http://old.nabble.com/file/p27838821/Fig%2B1%2BUSRP%2Bv2.jpg
>>
>> As mentioned above we are using 4 USRPs to receive a signal from a single
>> source. We wish to retain the phase information of this signal between
>> boxes
>> due to the different positions of the antennas. We feed all 4 boxes with
>> a
>> clock reference signal (10MHz, 1.5Vpk-pk), so that their internal clocks
>> should be locked in phase with respect to each other. Are the internally
>> generated carriers generated using this clock as a phase reference, i.e.
>> is
>> it correct, that this should also make all the internally generated
>> carriers
>> have zero phase difference between the boxes instead of locking to the
>> phases of the incoming signals (see Figure 2.)?
>> http://old.nabble.com/file/p27838821/Fig%2B2%2BUSRP%2Bv2.jpg
>>
>> However, when we observe the internal clocks of 4 USRPs they are phase
>> locked with respect to one another, but THERE IS A PHASE DIFFERENCE
>> BETWEEN
>> THEM, which is constant for a given power cycle. Does this imply that the
>> phases of the internally generated carriers are locked to one another,
>> but
>> also with some NON 0 PHASE difference, i.e. that our actual system looks
>> like Figure 3?
>> http://old.nabble.com/file/p27838821/Fig%2B3%2BUSRP%2Bv3.jpg
>>
>> Thanks,
>> Valentin.
> 
> 
> I assume you are using all USRP2s.  There are multiple sources of 
> ambiguity here.
> 
> First, unless you are using a common PPS signal to all systems, using 
> sync_on_pps, your time samples won't be aligned.  Think of it this way 
> -- everyone's watch is running at the same speed, but everybody thinks 
> the time is different because you haven't coordinated.  That's what the 
> PPS is for
> 
> Second, and this is what Eric mentioned, the PLLs on the daughterboards 
> will all be locked to the same reference, but they can have an arbitrary 
> offset which will change every time you tune.  The important thing is 
> that the relative phases don't change with time.  This means you can do 
> MIMO operations, but phased-arrays will require you to calibrate every 
> time.  You can use the TX side of the RFX-series as a signal generate to 
> do this, but it will take some software.
> 
> You didn't tell us what daughterboards you are using.  The ones with the 
> integer-N PLLs (DBSRX, RFX-series) will have a finite number of 
> possibilities for that phase difference, usually less than 25, and you 
> can tune in such a way that there is no ambiguity if you are careful. 
> The fractional-N ones (XCVR2450, WBX) will have an effectively infinite 
> number of possibilities, but you can still measure it and compensate.
> 
> If you are just using the BasicRX or LFRX then you don't have this 
> problem, you just need to align their DDC oscillators using PPS.
> 
> Matt
> 
> 
> 
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