Marcus,
First of all, thanks for responding so quickly.
I looked on the USRP2 faq and I did see that the DAC rate was listed as
400 MS/s, but later on in the faq it says:
The FPGA talks to the DAC at 100 MS/s just like it talks to the ADC
at 100 MS/s. The interpolation from 100 MS/s to 400 MS/s happens inside
the DAC chip itself. Unless you are doing something fancy, you can think
of the
DAC as operating at 100 MS/s.
If I am just misunderstanding that and I do need to use 400 MS/s as my
DAC rate, is there some upper limit to what the samples per symbol value
can be? Since interpolation has to be between 4 and 512, the lowest
possible values that I could use to get a 10kbps would be 80 samples per
symbol with 500 as my interpolation rate.