Re: [Discuss-gnuradio] FPGA usage in USRP E100

[Matt Ettus]

On 01/24/2011 10:30 AM, Alexander Chemeris wrote:
> Hi all,
>
> Is there any high-level description of what processing is done in FPGA
> in E100 and is there any optional blocks which can be removed? I see
> that even aeMB is present in the project - is it used or it is not
> compiled in?

There is no aeMB in the E100, although it is in the Makefiles since we 
share the makefiles among the various projects.  The current E100 FPGA 
has a similar structure to the USRP2 except that the aeMB is replaced by 
an interface to the GPMC.  So there are the usual digital up and 
downconverters, decimators, and interpolators for DSP, and SPI, I2C, 
wishbone, etc. for control.  The u1e_core.v file is the place to look 
for the top level.

> I need to understand how much resource is left for custom DSP
> processing in the FPGA. We're working on an (open-source) WiMAX
> receiver and want to offload a lot of work to FPGA. But from design
> summary (below) it looks like FPGA is pretty much crowded already.

The logic area is 60-70% free.  You should ignore the "number of 
occupied slices" metric as that is not really meaningful.

81% of the DSP units and 52% of the memory are free.  The bulk of the 
memory currently used is for buffering and can be trimmed if you need 
more of it.

Additionally, in March or April we will have the E110 which is the same 
except that it uses an even bigger FPGA, the -3400 version.

Matt


> Design Summary
> --------------
> Number of errors:      0
> Number of warnings: 9773
> Logic Utilization:
>    Number of Slice Flip Flops:         9,809 out of  33,280   29%
>    Number of 4 input LUTs:            12,582 out of  33,280   37%
> Logic Distribution:
>    Number of occupied Slices:          8,618 out of  16,640   51%
>      Number of Slices containing only related logic:   8,618 out of   8,618 100%
>      Number of Slices containing unrelated logic:          0 out of   8,618   0%
>        *See NOTES below for an explanation of the effects of unrelated logic.
>    Total Number of 4 input LUTs:      13,252 out of  33,280   39%
>      Number used as logic:            11,239
>      Number used as a route-thru:        670
>      Number used as Shift registers:   1,343
>
>    The Slice Logic Distribution report is not meaningful if the design is
>    over-mapped for a non-slice resource or if Placement fails.
>
>    Number of bonded IOBs:                191 out of     309   61%
>      IOB Flip Flops:                     106
>      IOB Master Pads:                      1
>      IOB Slave Pads:                       1
>    Number of ODDR2s used:                 15
>      Number of DDR_ALIGNMENT = NONE       15
>      Number of DDR_ALIGNMENT = C0          0
>      Number of DDR_ALIGNMENT = C1          0
>    Number of BUFGMUXs:                     1 out of      24    4%
>    Number of DCMs:                         1 out of       8   12%
>    Number of DSP48As:                     16 out of      84   19%
>    Number of RAMB16BWERs:                 41 out of      84   48%
>
> Average Fanout of Non-Clock Nets:                3.25