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Hi everyone,
I thought I had a problem with my FPGA image, but the led F means that the FPGA
is well programed. The led E would mean that the FPGA have load the
firmware. I compiled the raw internet version of the FPGA with ISE 10.1
and i tried it with Raw Ethernet firmware with WBX.
So the problem is not compiling the code but the
code itself or the firmware. To be sure, is there anyone who could give me the
summary playback sequence of the firmware. How the FPGA loads the firmware in
RAM? Where are the source files of the firmware? I have to study them to
understand what goes wrong. Can it be the initialization of the block RAM
in the ucf files or everything else?
Gabriel
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