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[Discuss-gnuradio] Re: question about RFX2400


From: Malihe Ahmadi
Subject: [Discuss-gnuradio] Re: question about RFX2400
Date: Wed, 23 Feb 2011 14:07:03 -0700
User-agent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.13) Gecko/20101207 Thunderbird/3.1.7

Hi,

I have included this line in my python flowgraph:
sink.config_mimo(usrp2.MC_WE_LOCK_TO_SMA)
where sink is:
sink = usrp2.sink_32fc()
but I think USRP2 is not locked to the external reference clock since when I turn this ref clock generator off, there is no change in the spectrum of the output of USRP2. My understanding is that if USRP2 is locked to the ref clock, when I turn the clock off I should see no signal at the output of USRP2. can somebody please help me with this? How do I get the USRP2 to lock to the ref clock?

Thanks,
Malihe

On 1/6/2011 1:07 PM, Nick Foster wrote:
Malihe,

The USRP2 has a 10MHz reference clock input on an SMA connector on the
front panel. It accepts a sine or square wave input between 5dBm and
15dBm of amplitude. If you connect the same 10MHz source clock to two
USRP2s they will lock their 100MHz oscillators to this 10MHz clock and
thus they will not have an offset frequency from one another.

In order to enable the reference locking after 10MHz signals are
connected to both USRP2s, you can use
<usrp2_source_name>.config_mimo(usrp2.MC_WE_LOCK_TO_SMA) command from
your Python flowgraph.

The Doxygen HTML output in gnuradio/docs/doxygen/html will contain API
information if you need more specifics.

--n

On Thu, 2011-01-06 at 09:03 -0700, Malihe Ahmadi wrote:
Hi Nick,
can you please explain more about the requirement of the external clock? 
and what do you mean by enabling reference clock? I need more 
information..., any doc I can read?

Thanks,
Malihe

On 04/01/2011 7:38 PM, Nick Foster wrote:
On Tue, 2011-01-04 at 19:25 -0700, Malihe Ahmadi wrote:
Hi,

I am testing a transceiver link in ISM band using two USRP2+RFX2400, one
configured as TX and the other one as RX. I would like to test my own
FPGA program, so for now I have your FPGA codes in which I only changed
the signal driving the DAC in TX to be an square wave (+8191 or -8192)
with frequency about 400Hz. At the RX side, I am looking (using an
oscilloscope) at the input to the ADC and what I see is quite like my
square wave modulated with a carrier of couple of MHz. I looked at the
schematic of RFX2400 and I didn't find any PLL or clock recovery
circuitry! so I wonder how the frequency offset at RX could be avoided?

Regards,
Malihe
In a software-defined radio, frequency estimation and clock recovery are
typically done in software, to keep the hardware general-purpose enough
for many different uses. You can either synchronize the two USRP2s by
using a common 10MHz reference input to both devices (and enabling the
reference lock), or deal with the inevitable frequency mismatch in
software.

--n




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