On Sat, Apr 16, 2011 at 7:23 PM, Marcus D. Leech
<address@hidden> wrote:
I'm looking for opinions about whether doing a single-stage, N=2 decimator in software is practical for
sample rates of ~100Msps. Assume reasonably-modern X86-64 hardware, and R=[2..500].
It looks like the integrator stage could be reasonably lightweight, and the comb stage for N=2 could also be
quite lightweight.
Assume that input words are 10 to 12 bits.
It looks like bit growth wouldn't be much of an issue, because it's single-stage.
--
Marcus Leech
Principal Investigator
Shirleys Bay Radio Astronomy Consortium
http://www.sbrac.org
My guess is that, yes, you can probably get those speeds from a CIC in software. You're right, it's not very complicated, so, considering other numbers I've seen on various other SDR stuff people have done, I think it's doable. You might have to resort to SIMD programming to really get there, though. Then again, that's what Volk is for :)
Tom