On Mon, Mar 5, 2012 at 9:26 AM, David Knox
<address@hidden> wrote:
> I just don't want to loose all the flexibility of software by moving the
> critical but interesting things to hardware.
>
> (* But of course, it all depends upon your goals. *)
George (and others),
I think that the above statement is the basic
issue here and seems to summarize the issues with offering a 'solution for
everyone'; although, offering to do this is still noble sentiment from you,
George. I have been using the USRP1 for a few years now, using code based
on the old deprecated mblock code (and your code too!) and there have been a
few times when I have wondered about whether I needed to crack open the FPGA
code or not... and suffer through the re-fitting and then the required
timing verification that this would require above and beyond verifying any
functional changes I was considering in Verilog.
Thanks David! This kind of thing can impact the design of what I build. What in particular were you thinking about opening up the FPGA to modify that you felt it wasn't flexible enough?