Re: [Discuss-gnuradio] Arbitrary ADC resolution at the receiver

[Marcus Müller]

Hi Leo,

well, I'd argue that reducing receiver complexity doesn't really happen
when you start changing the FPGA with respect to dev effort; I can see
your DDC numerical accuracy point, though.
However, how would reducing the ADC resolution make artifacts more
noticable? As you get ca -6dB theoretical SNR with each bit you cut at
the ADC, errors in the DDC should become less relevant, not more.

 Best Regards,
Marcus
On 01.07.2014 14:54, Leonardo S. Cardoso wrote:
> Hi Marcus,
>
> There are several reasons why we would like to avoid reducing the
> resolution in software: 1. Reduce receiver complexity; 2. Capture any
> artifact of the DDC with respect to the reduction of the resolution.
>
> Frankly speaking, I'm not sure any of these arguments are defendable to
> impose a resolution control at the ADC or even the ADC-FPGA interface. If
> it isn't, then I agree it is much simple to do it in soft.
>
> BR,
>
> Leo
>
> Leonardo S. Cardoso
> address@hidden
>
>
> On Mon, Jun 30, 2014 at 5:46 PM, Marcus Müller <address@hidden>
> wrote:
>
>>  Just out of curiosity: Why would you want to reduce the ADC resolution?
>> Most of the effects introduced can be simulated in GNU Radio, e.g. by
>> converting a float stream to integer and dividing it by a constant power of
>> two.
>>
>> Greetings,
>> Marcus
>>
>> On 30.06.2014 16:59, Leonardo S. Cardoso wrote:
>>
>> Yes, 14 bits... mistyped the ADC resolution...
>>
>> Thanks, Matt. I'll investigate this idea...
>>
>> Leonardo S. address@hidden
>>
>>
>> On Mon, Jun 30, 2014 at 4:46 PM, Matt Ettus <address@hidden> 
>> <address@hidden> wrote:
>>
>>
>>  The n200 and n210 have 14 bit ADCs.
>>
>> In any case, you can fake fewer bits by zeroing the low order bits in the
>> fpga.
>>
>> Matt
>> On Jun 30, 2014 10:38 AM, "Leonardo S. Cardoso" <address@hidden> 
>> <address@hidden> wrote:
>>
>>
>>  Hello everyone,
>>
>> I excuse myself on advance by my noob question...
>>
>> I have an N210 with an SBX front end, and I want to experiment with
>> decoding signals at a lower resolution, rather than the default 12 bits
>> provided by the N210 ADCs. Does anyone know if (and how) can I limit the
>> resolution of the ADCs arbitrarily?
>>
>> I am aware that I can reduce the resolution afterwards, mapping the
>> signals to a lower resolution in base band, but I'd really like to do that
>> before the DDC at the FPGA.
>>
>> Cheers to everyone!
>>
>> Leonardo S. address@hidden
>>
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