Hi,
I am using URSPN210 series, have few questions regarding the clocking schemes for this USRP N210. In the website, its mentioned
USRP2 and N200/N210 have fixed 100MHz clock which can't be tuned and do not have option to use external clock.
We would like to use a different clock rate (49.2MHz) instead of the fixed 100MHz that is generated from the Reference and system clock generation circuit( I think all these clocks i.e fpga clock, TX/RX clock for the RF boaord ADC/DAC
clock are generated by the AD9510 that has on chip PLL core and multi ouput clock distribution function). An external oscillator (U27 or external reference clock) is phase locked to a reference input reference frequency clock of the AD9510.
In the USRP N210 FPGA Code can we program the divider values of AD9510 over the SPI interface so that the output clock are not fixed?
We would like to be compatible with our internal Radio
waveform rates and frequencies.
Thanks.