... to clarify my recent post, I have these questions:
(1) Why does the host experience so many overflows at such a low
sampling rate? (Maybe ISE synthesized out a section of the Tx chain of
the FPGA when it saw that sample_tx is not used?)
(2) Why doesn't the loopback of Rx to Tx work in the FPGA? Has anyone
tried this?
(3) Is there a better/easier way of setting up the Rx and Tx chain?
Should there be something between the USRP source and USRP sink blocks?
Thanks,
-ben
On Wed, Mar 4, 2015 at 4:13 PM, Ben Lapointe <address@hidden
<mailto:address@hidden>> wrote:
Hi,
I'm still having trouble getting a Rx/Tx loopback to work in the
E310. I modified radio.v to do the loopback. I created a simple
top_block.py in gnuradio-companion with a USRP source connected to a
USRP sink to configure the Rx and Tx channels of the E310. sample
frequency 1MS/s, center frequency 310 MHz, gain 30.
When I run top_block.py I don't see RF signal at the TRX-A port, and
the output to the screen shows a continuous stream of underflows
(below is the output). I have a 310 MHz CW at -20dBm going into
RX2-A of the E310. Below is the console output when I run
top_block.py a description of my setup.
address@hidden:~/bens_stuff# ./top_block.py
linux; GNU C++ version 4.9.1; Boost_105600; UHD_003.008.002-0-unknown
-- Loading FPGA image: /home/root/bens_stuff/usrp_e310_fpga.bit... done
-- Detecting internal GPSDO.... found
-- Initializing core control...
-- Performing register loopback test... pass
-- Performing register loopback test... pass
-- Performing register loopback test... pass
-- Performing CODEC loopback test... pass
-- Performing CODEC loopback test... pass
-- Setting time source to internal
-- Asking for clock rate 32 MHz
-- Actually got clock rate 32 MHz
-- Performing timer loopback test... pass
-- Performing timer loopback test... pass
-- Successfully tuned to 310.000000 MHz
--
-- Successfully tuned to 310.000000 MHz
--
Press Enter to quit: UUUUUUUUUUUUUUUUUUUUUUUUUUUUU (...continues
forever)
My Setup:
I made a new SD card with sdimage-gnuradio-dev.direct.xz from
http://files.ettus.com/e3xx_images/beta/dizzy-test/
I checked the newest FPGA code out of GIT
I added the following lines to radio.v:
wire [15:0] user_I = sample_rx[31:16];
wire [15:0] user_Q = sample_rx[15:0];
I modified the duc_chain to take in {user_i,user_q} instead of sample_tx
The host build and the FPGA build are now at compatibility level 6.
I appreciate any advice, thanks,
-Ben
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