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[Emacs-diffs] /srv/bzr/emacs/emacs-24 r108114: Merge verilog-mode.el fro
|
From: |
Stefan Monnier |
|
Subject: |
[Emacs-diffs] /srv/bzr/emacs/emacs-24 r108114: Merge verilog-mode.el from upstream. |
|
Date: |
Fri, 02 Nov 2012 02:33:56 -0000 |
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User-agent: |
Bazaar (2.5.0) |
------------------------------------------------------------
revno: 108114
author: Wilson Snyder <address@hidden>, Michael McNamara <address@hidden>
committer: Stefan Monnier <address@hidden>
branch nick: trunk
timestamp: Thu 2012-05-03 15:23:55 -0400
message:
Merge verilog-mode.el from upstream.
* progmodes/verilog-mode.el (font-lock-keywords):
Fix mis-highligting auto. Reported by Craig Barner.
(verilog-auto, verilog-auto-undef): Add AUTOUNDEF to remove
defines from global name space. Reported by Dan Dever.
(verilog-auto-reset, verilog-auto-reset-widths)
(verilog-auto-tieoff): Support using unbased numbers for
AUTORESET and AUTOTIEOFF.
(verilog-submit-bug-report): Update variable list.
(verilog-read-auto-params): Fix AUTOINPUT regexps containing
parenthesis from not matching. Reported by Michael Rytting.
(verilog-auto-template-lint): Fix hash error when linting modules
with no used templates.
(verilog-warn, verilog-warn-error)
(verilog-warn-fatal): When non-interactive report multiple
warnings before exiting. Suggested by Brad Dobbie.
(verilog-auto-template-lint, verilog-auto-template-warn-unused)
(verilog-read-auto-template): Add `verilog-auto-template-warn-unused'
to report unused template errors. Reported by Brad Dobbie.
(verilog-read-decls): Fix AUTOWIRE etc on supply0, supply1 type
nets, bug438. Reported by Vns Blore.
(verilog-auto-inout-module, verilog-auto-reg)
(verilog-read-decls, verilog-read-sub-decls-sig)
(verilog-signals-edit-wire-reg, verilog-signals-with):
Fix passing of Verilog data types in ANSI input/output ports
such as "output logic" into the AUTOs. Special case "wire" and
"reg" for backwards compatibility presuming Verilog 2001.
(verilog-auto-ascii-enum): Add "auto enum" as alias.
(verilog-preprocess): Fix replication of preprocess output.
Reported by Brad Dobbie.
(verilog-auto-inst-interfaced-ports):
Create verilog-auto-inst-interfaced-ports, bug429.
Reported by Julian Gorfajn.
(verilog-after-save-font-hook)
(verilog-before-save-font-hook): New variable.
(verilog-modi-cache-results, verilog-save-font-mod-hooked)
(verilog-save-font-mods): Wrap disabling fontification, reported
by David Rogoff.
(verilog-do-indent, verilog-pretty-declarations-auto)
(verilog-sk-def-reg): Fix obeying `verilog-auto-lineup', bug305.
Reported by Pierre-David Pfister.
(verilog-set-auto-endcomments): Fix endtask auto comments outside
of class declarations, bug292. Reported by Kevin Heilman.
(verilog-read-decls): Fix 'parameter type' not appearing in
AUTOINSTPARAM, bug340. Reported by Jonathan Greenlaw.
(verilog-auto-logic): Fix when AUTOLOGIC present to properly do
AUTOINPUTs, bug411. Reported by Jonathan Greenlaw.
(verilog-read-auto-lisp): Avoid syntax-ppss warning on AUTOLISP.
Reported by David Kravitz.
* progmodes/verilog-mode.el (verilog-pretty-expr): Don't line up
assignment with tests in ifs and for loops.
(verilog-extended-complete-re, verilog-complete-reg): Change so
that DPI inport functions don't look like fuction declarations.
(verilog-pretty-expr): Don't line up assignment
operations to the test and increment in if and for loops
(verilog-extended-complete-re, verilog-complete-reg): Change so
that DPI inport functions don't look like fuction declarations
modified:
lisp/ChangeLog
lisp/progmodes/verilog-mode.el
=== modified file 'lisp/ChangeLog'
--- a/lisp/ChangeLog 2012-05-03 06:57:54 +0000
+++ b/lisp/ChangeLog 2012-05-03 19:23:55 +0000
@@ -1,3 +1,65 @@
+2012-05-03 Wilson Snyder <address@hidden>
+
+ * progmodes/verilog-mode.el (font-lock-keywords):
+ Fix mis-highligting auto. Reported by Craig Barner.
+ (verilog-auto, verilog-auto-undef): Add AUTOUNDEF to remove
+ defines from global name space. Reported by Dan Dever.
+ (verilog-auto-reset, verilog-auto-reset-widths)
+ (verilog-auto-tieoff): Support using unbased numbers for
+ AUTORESET and AUTOTIEOFF.
+ (verilog-submit-bug-report): Update variable list.
+ (verilog-read-auto-params): Fix AUTOINPUT regexps containing
+ parenthesis from not matching. Reported by Michael Rytting.
+ (verilog-auto-template-lint): Fix hash error when linting modules
+ with no used templates.
+ (verilog-warn, verilog-warn-error)
+ (verilog-warn-fatal): When non-interactive report multiple
+ warnings before exiting. Suggested by Brad Dobbie.
+ (verilog-auto-template-lint, verilog-auto-template-warn-unused)
+ (verilog-read-auto-template): Add `verilog-auto-template-warn-unused'
+ to report unused template errors. Reported by Brad Dobbie.
+ (verilog-read-decls): Fix AUTOWIRE etc on supply0, supply1 type
+ nets, bug438. Reported by Vns Blore.
+ (verilog-auto-inout-module, verilog-auto-reg)
+ (verilog-read-decls, verilog-read-sub-decls-sig)
+ (verilog-signals-edit-wire-reg, verilog-signals-with):
+ Fix passing of Verilog data types in ANSI input/output ports
+ such as "output logic" into the AUTOs. Special case "wire" and
+ "reg" for backwards compatibility presuming Verilog 2001.
+ (verilog-auto-ascii-enum): Add "auto enum" as alias.
+ (verilog-preprocess): Fix replication of preprocess output.
+ Reported by Brad Dobbie.
+ (verilog-auto-inst-interfaced-ports):
+ Create verilog-auto-inst-interfaced-ports, bug429.
+ Reported by Julian Gorfajn.
+ (verilog-after-save-font-hook)
+ (verilog-before-save-font-hook): New variable.
+ (verilog-modi-cache-results, verilog-save-font-mod-hooked)
+ (verilog-save-font-mods): Wrap disabling fontification, reported
+ by David Rogoff.
+ (verilog-do-indent, verilog-pretty-declarations-auto)
+ (verilog-sk-def-reg): Fix obeying `verilog-auto-lineup', bug305.
+ Reported by Pierre-David Pfister.
+ (verilog-set-auto-endcomments): Fix endtask auto comments outside
+ of class declarations, bug292. Reported by Kevin Heilman.
+ (verilog-read-decls): Fix 'parameter type' not appearing in
+ AUTOINSTPARAM, bug340. Reported by Jonathan Greenlaw.
+ (verilog-auto-logic): Fix when AUTOLOGIC present to properly do
+ AUTOINPUTs, bug411. Reported by Jonathan Greenlaw.
+ (verilog-read-auto-lisp): Avoid syntax-ppss warning on AUTOLISP.
+ Reported by David Kravitz.
+
+2012-05-03 Michael McNamara <address@hidden>
+
+ * progmodes/verilog-mode.el (verilog-pretty-expr): Don't line up
+ assignment with tests in ifs and for loops.
+ (verilog-extended-complete-re, verilog-complete-reg): Change so
+ that DPI inport functions don't look like fuction declarations.
+ (verilog-pretty-expr): Don't line up assignment
+ operations to the test and increment in if and for loops
+ (verilog-extended-complete-re, verilog-complete-reg): Change so
+ that DPI inport functions don't look like fuction declarations
+
2012-05-03 Kenichi Handa <address@hidden>
* mail/rmailmm.el (rmail-show-mime): Catch an error caused by text
=== modified file 'lisp/progmodes/verilog-mode.el'
--- a/lisp/progmodes/verilog-mode.el 2012-04-22 13:58:00 +0000
+++ b/lisp/progmodes/verilog-mode.el 2012-05-03 19:23:55 +0000
@@ -123,9 +123,9 @@
;;; Code:
;; This variable will always hold the version number of the mode
-(defconst verilog-mode-version "725"
+(defconst verilog-mode-version "800"
"Version of this Verilog mode.")
-(defconst verilog-mode-release-date "2011-11-27-GNU"
+(defconst verilog-mode-release-date "2012-04-23-GNU"
"Release date of this Verilog mode.")
(defconst verilog-mode-release-emacs t
"If non-nil, this version of Verilog mode was released with Emacs itself.")
@@ -415,7 +415,10 @@
:group 'verilog-mode)
(defvar verilog-debug nil
- "If set, enable debug messages for `verilog-mode' internals.")
+ "Non-nil means enable debug messages for `verilog-mode' internals.")
+
+(defvar verilog-warn-fatal nil
+ "Non-nil means `verilog-warn-error' warnings are fatal `error's.")
(defcustom verilog-linter
"echo 'No verilog-linter set, see \"M-x describe-variable verilog-linter\"'"
@@ -524,6 +527,8 @@
(const :tag "Line up Declarations" declarations)
(function :tag "Other"))
:group 'verilog-mode-indent )
+(put 'verilog-auto-lineup 'safe-local-variable
+ '(lambda (x) (memq x '(nil all assignments declarations))))
(defcustom verilog-indent-level 3
"Indentation of Verilog statements with respect to containing block."
@@ -600,40 +605,39 @@
(put 'verilog-case-indent 'safe-local-variable 'integerp)
(defcustom verilog-auto-newline t
- "True means automatically newline after semicolons."
+ "Non-nil means automatically newline after semicolons."
:group 'verilog-mode-indent
:type 'boolean)
(put 'verilog-auto-newline 'safe-local-variable 'verilog-booleanp)
(defcustom verilog-auto-indent-on-newline t
- "True means automatically indent line after newline."
+ "Non-nil means automatically indent line after newline."
:group 'verilog-mode-indent
:type 'boolean)
(put 'verilog-auto-indent-on-newline 'safe-local-variable 'verilog-booleanp)
(defcustom verilog-tab-always-indent t
- "True means TAB should always re-indent the current line.
+ "Non-nil means TAB should always re-indent the current line.
A nil value means TAB will only reindent when at the beginning of the line."
:group 'verilog-mode-indent
:type 'boolean)
(put 'verilog-tab-always-indent 'safe-local-variable 'verilog-booleanp)
(defcustom verilog-tab-to-comment nil
- "True means TAB moves to the right hand column in preparation for a comment."
+ "Non-nil means TAB moves to the right hand column in preparation for a
comment."
:group 'verilog-mode-actions
:type 'boolean)
(put 'verilog-tab-to-comment 'safe-local-variable 'verilog-booleanp)
(defcustom verilog-indent-begin-after-if t
- "If true, indent begin statements following if, else, while, for and repeat.
+ "Non-nil means indent begin statements following if, else, while, etc.
Otherwise, line them up."
:group 'verilog-mode-indent
:type 'boolean)
(put 'verilog-indent-begin-after-if 'safe-local-variable 'verilog-booleanp)
-
(defcustom verilog-align-ifelse nil
- "If true, align `else' under matching `if'.
+ "Non-nil means align `else' under matching `if'.
Otherwise else is lined up with first character on line holding matching if."
:group 'verilog-mode-indent
:type 'boolean)
@@ -648,7 +652,7 @@
(put 'verilog-minimum-comment-distance 'safe-local-variable 'integerp)
(defcustom verilog-highlight-p1800-keywords nil
- "True means highlight words newly reserved by IEEE-1800.
+ "Non-nil means highlight words newly reserved by IEEE-1800.
These will appear in `verilog-font-lock-p1800-face' in order to gently
suggest changing where these words are used as variables to something else.
A nil value means highlight these words as appropriate for the SystemVerilog
@@ -659,7 +663,7 @@
(put 'verilog-highlight-p1800-keywords 'safe-local-variable 'verilog-booleanp)
(defcustom verilog-highlight-grouping-keywords nil
- "True means highlight grouping keywords 'begin' and 'end' more dramatically.
+ "Non-nil means highlight grouping keywords 'begin' and 'end' more
dramatically.
If false, these words are in the `font-lock-type-face'; if True then they are
in
`verilog-font-lock-ams-face'. Some find that special highlighting on these
grouping constructs allow the structure of the code to be understood at a
glance."
@@ -668,7 +672,7 @@
(put 'verilog-highlight-grouping-keywords 'safe-local-variable
'verilog-booleanp)
(defcustom verilog-highlight-modules nil
- "True means highlight module statements for `verilog-load-file-at-point'.
+ "Non-nil means highlight module statements for `verilog-load-file-at-point'.
When true, mousing over module names will allow jumping to the
module definition. If false, this is not supported. Setting
this is experimental, and may lead to bad performance."
@@ -677,7 +681,7 @@
(put 'verilog-highlight-modules 'safe-local-variable 'verilog-booleanp)
(defcustom verilog-highlight-includes t
- "True means highlight module statements for `verilog-load-file-at-point'.
+ "Non-nil means highlight module statements for `verilog-load-file-at-point'.
When true, mousing over include file names will allow jumping to the
file referenced. If false, this is not supported."
:group 'verilog-mode-indent
@@ -689,7 +693,7 @@
Set this to \"wire\" if the Verilog code uses \"`default_nettype
none\". Note using `default_nettype none isn't recommended practice; this
mode is experimental."
- :version "24.1"
+ :version "24.1" ;; rev670
:group 'verilog-mode-actions
:type 'boolean)
(put 'verilog-auto-declare-nettype 'safe-local-variable `stringp)
@@ -697,27 +701,27 @@
(defcustom verilog-auto-wire-type nil
"Non-nil specifies the data type to use with `verilog-auto-wire' etc.
Set this to \"logic\" for SystemVerilog code, or use `verilog-auto-logic'."
- :version "24.1"
+ :version "24.1" ;; rev673
:group 'verilog-mode-actions
:type 'boolean)
(put 'verilog-auto-wire-type 'safe-local-variable `stringp)
(defcustom verilog-auto-endcomments t
- "True means insert a comment /* ... */ after 'end's.
+ "Non-nil means insert a comment /* ... */ after 'end's.
The name of the function or case will be set between the braces."
:group 'verilog-mode-actions
:type 'boolean)
(put 'verilog-auto-endcomments 'safe-local-variable 'verilog-booleanp)
(defcustom verilog-auto-delete-trailing-whitespace nil
- "True means to `delete-trailing-whitespace' in `verilog-auto'."
- :version "24.1"
+ "Non-nil means to `delete-trailing-whitespace' in `verilog-auto'."
+ :version "24.1" ;; rev703
:group 'verilog-mode-actions
:type 'boolean)
(put 'verilog-auto-delete-trailing-whitespace 'safe-local-variable
'verilog-booleanp)
(defcustom verilog-auto-ignore-concat nil
- "True means ignore signals in {...} concatenations for AUTOWIRE etc.
+ "Non-nil means ignore signals in {...} concatenations for AUTOWIRE etc.
This will exclude signals referenced as pin connections in {...}
from AUTOWIRE, AUTOOUTPUT and friends. This flag should be set
for backward compatibility only and not set in new designs; it
@@ -727,7 +731,7 @@
(put 'verilog-auto-ignore-concat 'safe-local-variable 'verilog-booleanp)
(defcustom verilog-auto-read-includes nil
- "True means to automatically read includes before AUTOs.
+ "Non-nil means to automatically read includes before AUTOs.
This will do a `verilog-read-defines' and `verilog-read-includes' before
each AUTO expansion. This makes it easier to embed defines and includes,
but can result in very slow reading times if there are many or large
@@ -750,15 +754,15 @@
:type '(choice (const nil) (const ask) (const detect) (const force)))
(defcustom verilog-auto-star-expand t
- "Non-nil indicates to expand a SystemVerilog .* instance ports.
-They will be expanded in the same way as if there was a AUTOINST in the
+ "Non-nil means to expand SystemVerilog .* instance ports.
+They will be expanded in the same way as if there was an AUTOINST in the
instantiation. See also `verilog-auto-star' and `verilog-auto-star-save'."
:group 'verilog-mode-actions
:type 'boolean)
(put 'verilog-auto-star-expand 'safe-local-variable 'verilog-booleanp)
(defcustom verilog-auto-star-save nil
- "Non-nil indicates to save to disk SystemVerilog .* instance expansions.
+ "Non-nil means save to disk SystemVerilog .* instance expansions.
A nil value indicates direct connections will be removed before saving.
Only meaningful to those created due to `verilog-auto-star-expand' being set.
@@ -964,7 +968,7 @@
(put 'verilog-active-low-regexp 'safe-local-variable 'stringp)
(defcustom verilog-auto-sense-include-inputs nil
- "If true, AUTOSENSE should include all inputs.
+ "Non-nil means AUTOSENSE should include all inputs.
If nil, only inputs that are NOT output signals in the same block are
included."
:group 'verilog-mode-auto
@@ -972,7 +976,7 @@
(put 'verilog-auto-sense-include-inputs 'safe-local-variable 'verilog-booleanp)
(defcustom verilog-auto-sense-defines-constant nil
- "If true, AUTOSENSE should assume all defines represent constants.
+ "Non-nil means AUTOSENSE should assume all defines represent constants.
When true, the defines will not be included in sensitivity lists. To
maintain compatibility with other sites, this should be set at the bottom
of each Verilog file that requires it, rather than being set globally."
@@ -981,28 +985,36 @@
(put 'verilog-auto-sense-defines-constant 'safe-local-variable
'verilog-booleanp)
(defcustom verilog-auto-reset-blocking-in-non t
- "If true, AUTORESET will reset those signals which were
-assigned with blocking assignments (=) even in a block with
-non-blocking assignments (<=).
+ "Non-nil means AUTORESET will reset blocking statements.
+When true, AUTORESET will reset in blocking statements those
+signals which were assigned with blocking assignments (=) even in
+a block with non-blocking assignments (<=).
If nil, all blocking assigned signals are ignored when any
non-blocking assignment is in the AUTORESET block. This allows
blocking assignments to be used for temporary values and not have
those temporaries reset. See example in `verilog-auto-reset'."
- :version "24.1"
+ :version "24.1" ;; rev718
:type 'boolean
:group 'verilog-mode-auto)
(put 'verilog-auto-reset-blocking-in-non 'safe-local-variable
'verilog-booleanp)
(defcustom verilog-auto-reset-widths t
- "If true, AUTORESET should determine the width of signals.
+ "True means AUTORESET should determine the width of signals.
This is then used to set the width of the zero (32'h0 for example). This
is required by some lint tools that aren't smart enough to ignore widths of
-the constant zero. This may result in ugly code when parameters determine
-the MSB or LSB of a signal inside an AUTORESET."
+the constant zero. This may result in ugly code when parameters determine
+the MSB or LSB of a signal inside an AUTORESET.
+
+If nil, AUTORESET uses \"0\" as the constant.
+
+If 'unbased', AUTORESET used the unbased unsized literal \"'0\"
+as the constant. This setting is strongly recommended for
+SystemVerilog designs."
:type 'boolean
:group 'verilog-mode-auto)
-(put 'verilog-auto-reset-widths 'safe-local-variable 'verilog-booleanp)
+(put 'verilog-auto-reset-widths 'safe-local-variable
+ '(lambda (x) (memq x '(nil t unbased))))
(defcustom verilog-assignment-delay ""
"Text used for delays in delayed assignments. Add a trailing space if set."
@@ -1011,7 +1023,7 @@
(put 'verilog-assignment-delay 'safe-local-variable 'stringp)
(defcustom verilog-auto-arg-sort nil
- "If set, AUTOARG signal names will be sorted, not in declaration order.
+ "Non-nil means AUTOARG signal names will be sorted, not in declaration order.
Declaration order is advantageous with order based instantiations
and is the default for backward compatibility. Sorted order
reduces changes when declarations are moved around in a file, and
@@ -1023,7 +1035,7 @@
(put 'verilog-auto-arg-sort 'safe-local-variable 'verilog-booleanp)
(defcustom verilog-auto-inst-dot-name nil
- "If true, when creating ports with AUTOINST, use .name syntax.
+ "Non-nil means when creating ports with AUTOINST, use .name syntax.
This will use \".port\" instead of \".port(port)\" when possible.
This is only legal in SystemVerilog files, and will confuse older
simulators. Setting `verilog-auto-inst-vector' to nil may also
@@ -1033,7 +1045,7 @@
(put 'verilog-auto-inst-dot-name 'safe-local-variable 'verilog-booleanp)
(defcustom verilog-auto-inst-param-value nil
- "If set, AUTOINST will replace parameters with the parameter value.
+ "Non-nil means AUTOINST will replace parameters with the parameter value.
If nil, leave parameters as symbolic names.
Parameters must be in Verilog 2001 format #(...), and if a parameter is not
@@ -1041,7 +1053,7 @@
be replaced, and will remain symbolic.
For example, imagine a submodule uses parameters to declare the size of its
-inputs. This is then used by a upper module:
+inputs. This is then used by an upper module:
module InstModule (o,i);
parameter WIDTH;
@@ -1070,20 +1082,20 @@
(put 'verilog-auto-inst-param-value 'safe-local-variable 'verilog-booleanp)
(defcustom verilog-auto-inst-sort nil
- "If set, AUTOINST signal names will be sorted, not in declaration order.
+ "Non-nil means AUTOINST signals will be sorted, not in declaration order.
Also affects AUTOINSTPARAM. Declaration order is the default for
backward compatibility, and as some teams prefer signals that are
declared together to remain together. Sorted order reduces
changes when declarations are moved around in a file.
See also `verilog-auto-arg-sort'."
- :version "24.1"
+ :version "24.1" ;; rev688
:group 'verilog-mode-auto
:type 'boolean)
(put 'verilog-auto-inst-sort 'safe-local-variable 'verilog-booleanp)
(defcustom verilog-auto-inst-vector t
- "If true, when creating default ports with AUTOINST, use bus subscripts.
+ "Non-nil means when creating default ports with AUTOINST, use bus subscripts.
If nil, skip the subscript when it matches the entire bus as declared in
the module (AUTOWIRE signals always are subscripted, you must manually
declare the wire to have the subscripts removed.) Setting this to nil may
@@ -1115,6 +1127,12 @@
:type 'integer)
(put 'verilog-auto-inst-column 'safe-local-variable 'integerp)
+(defcustom verilog-auto-inst-interfaced-ports t
+ "Non-nil means include interfaced ports in AUTOINST expansions."
+ :group 'verilog-mode-auto
+ :type 'boolean)
+(put 'verilog-auto-inst-interfaced-ports 'safe-local-variable
'verilog-booleanp)
+
(defcustom verilog-auto-input-ignore-regexp nil
"If set, when creating AUTOINPUT list, ignore signals matching this regexp.
See the \\[verilog-faq] for examples on using this."
@@ -1136,11 +1154,18 @@
:type 'string)
(put 'verilog-auto-output-ignore-regexp 'safe-local-variable 'stringp)
+(defcustom verilog-auto-template-warn-unused nil
+ "Non-nil means report warning if an AUTO_TEMPLATE line is not used.
+This feature is not supported before Emacs 21.1 or XEmacs 21.4."
+ :group 'verilog-mode-auto
+ :type 'boolean)
+(put 'verilog-auto-template-warn-unused 'safe-local-variable 'verilog-booleanp)
+
(defcustom verilog-auto-tieoff-declaration "wire"
- "Data type used for the declaration for AUTOTIEOFF. If \"wire\" then
-create a wire, if \"assign\" create an assignment, else the data type for
-variable creation."
- :version "24.1"
+ "Data type used for the declaration for AUTOTIEOFF.
+If \"wire\" then create a wire, if \"assign\" create an
+assignment, else the data type for variable creation."
+ :version "24.1" ;; rev713
:group 'verilog-mode-auto
:type 'string)
(put 'verilog-auto-tieoff-declaration 'safe-local-variable 'stringp)
@@ -1201,6 +1226,16 @@
:group 'verilog-mode-auto
:type 'hook)
+(defcustom verilog-before-save-font-hook nil
+ "Hook run before `verilog-save-font-mods' removes highlighting."
+ :group 'verilog-mode-auto
+ :type 'hook)
+
+(defcustom verilog-after-save-font-hook nil
+ "Hook run after `verilog-save-font-mods' restores highlighting."
+ :group 'verilog-mode-auto
+ :type 'hook)
+
(defvar verilog-imenu-generic-expression
'((nil
"^\\s-*\\(\\(m\\(odule\\|acromodule\\)\\)\\|primitive\\)\\s-+\\([a-zA-Z0-9_.:]+\\)"
4)
("*Vars*"
"^\\s-*\\(reg\\|wire\\)\\s-+\\(\\|\\[[^]]+\\]\\s-+\\)\\([A-Za-z0-9_]+\\)" 3))
@@ -1430,6 +1465,8 @@
:help "Help on AUTOSENSE - sensitivity lists for always
blocks"]
["AUTOTIEOFF" (describe-function 'verilog-auto-tieoff)
:help "Help on AUTOTIEOFF - tying off unused outputs"]
+ ["AUTOUNDEF" (describe-function 'verilog-auto-undef)
+ :help "Help on AUTOUNDEF - undefine all local defines"]
["AUTOUNUSED" (describe-function 'verilog-auto-unused)
:help "Help on AUTOUNUSED - terminating unused inputs"]
["AUTOWIRE" (describe-function 'verilog-auto-wire)
@@ -1552,7 +1589,7 @@
FIXEDCASE and LITERAL as in `replace-match`. STRING is what to replace.
The case (verilog-string-replace-matches \"o\" \"oo\" nil nil \"foobar\")
will break, as the o's continuously replace. xa -> x works ok though."
- ;; Hopefully soon to a emacs built-in
+ ;; Hopefully soon to an Emacs built-in
;; Also note \ in the replacement prevent multiple replacements; IE
;; (verilog-string-replace-matches "@" "\\\\([0-9]+\\\\)" nil nil
"address@hidden@")
;; Gives "wire\([0-9]+\)_@" not "wire\([0-9]+\)_\([0-9]+\)"
@@ -2401,7 +2438,6 @@
"\\|\\(\\<`[ou]vm_[a-z_]+_begin\\>\\)" ;28
"\\|\\(\\<`vmm_[a-z_]+_member_begin\\>\\)"
;;
-
))
(defconst verilog-end-block-ordered-rry
@@ -2629,11 +2665,11 @@
"endmodule" "endprimitive" "endinterface" "endpackage" "endprogram"
"endclass"
))))
(defconst verilog-disable-fork-re "\\(disable\\|wait\\)\\s-+fork\\>")
-(defconst verilog-extended-case-re
"\\(unique\\s-+\\|priority\\s-+\\)?case[xz]?")
+(defconst verilog-extended-case-re
"\\(\\(unique\\s-+\\|priority\\s-+\\)?case[xz]?\\)")
(defconst verilog-extended-complete-re
- (concat
"\\(\\<extern\\s-+\\|\\<\\(\\<pure\\>\\s-+\\)?virtual\\s-+\\|\\<protected\\s-+\\)*\\(\\<function\\>\\|\\<task\\>\\)"
-
"\\|\\(\\<typedef\\>\\s-+\\)*\\(\\<struct\\>\\|\\<union\\>\\|\\<class\\>\\)"
- "\\|\\(\\<import\\>\\s-+\\)?\"DPI-C\"\\s-+\\(function\\>\\|task\\>\\)"
+ (concat
"\\(\\(\\<extern\\s-+\\|\\<\\(\\<pure\\>\\s-+\\)?virtual\\s-+\\|\\<protected\\s-+\\)*\\(\\<function\\>\\|\\<task\\>\\)\\)"
+
"\\|\\(\\(\\<typedef\\>\\s-+\\)*\\(\\<struct\\>\\|\\<union\\>\\|\\<class\\>\\)\\)"
+
"\\|\\(\\(\\<import\\>\\s-+\\)?\\(\"DPI-C\"\\s-+\\)?\\(\\<pure\\>\\s-+\\)?\\(function\\>\\|task\\>\\)\\)"
"\\|" verilog-extended-case-re ))
(defconst verilog-basic-complete-re
(eval-when-compile
@@ -2645,9 +2681,7 @@
))))
(defconst verilog-complete-reg
(concat
- verilog-extended-complete-re
- "\\|"
- verilog-basic-complete-re))
+ verilog-extended-complete-re "\\|\\(" verilog-basic-complete-re "\\)"))
(defconst verilog-end-statement-re
(concat "\\(" verilog-beg-block-re "\\)\\|\\("
@@ -2764,7 +2798,8 @@
(defvar verilog-font-lock-keywords-3 nil
"Gaudy level highlighting for Verilog mode.
See also `verilog-font-lock-extra-types'.")
-(defvar verilog-font-lock-translate-off-face
+
+(defvar verilog-font-lock-translate-off-face
'verilog-font-lock-translate-off-face
"Font to use for translated off regions.")
(defface verilog-font-lock-translate-off-face
@@ -2842,8 +2877,8 @@
(verilog-pragma-keywords
(eval-when-compile
(verilog-regexp-opt
- '("surefire" "synopsys" "rtl_synthesis" "verilint" "leda" "0in") nil
- )))
+ '("surefire" "auto" "synopsys" "rtl_synthesis" "verilint" "leda"
"0in"
+ ) nil )))
(verilog-1800-2005-keywords
(eval-when-compile
@@ -2968,7 +3003,7 @@
(append verilog-font-lock-keywords-1
(list
;; Fontify pragmas
- (concat "\\(//\\s-*" verilog-pragma-keywords "\\s-.*\\)")
+ (concat "\\(//\\s-*\\(" verilog-pragma-keywords "\\)\\s-.*\\)")
;; Fontify escaped names
'("\\(\\\\\\S-*\\s-\\)" 0 font-lock-function-name-face)
;; Fontify macro definitions/ uses
@@ -3030,6 +3065,31 @@
after-change-functions)
(progn ,@body)))
+(defvar verilog-save-font-mod-hooked nil
+ "Local variable when inside a `verilog-save-font-mods' block.")
+(make-variable-buffer-local 'verilog-save-font-mod-hooked)
+
+(defmacro verilog-save-font-mods (&rest body)
+ "Execute BODY forms, disabling text modifications to allow performing BODY.
+Includes temporary disabling of `font-lock' to restore the buffer
+to full text form for parsing. Additional actions may be specified with
+`verilog-before-save-font-hook' and `verilog-after-save-font-hook'."
+ ;; Before version 20, match-string with font-lock returns a
+ ;; vector that is not equal to the string. IE if on "input"
+ ;; nil==(equal "input" (progn (looking-at "input") (match-string 0)))
+ `(let* ((hooked (unless verilog-save-font-mod-hooked
+ (verilog-run-hooks 'verilog-before-save-font-hook)
+ t))
+ (verilog-save-font-mod-hooked t)
+ (fontlocked (when (and (boundp 'font-lock-mode) font-lock-mode)
+ (font-lock-mode 0)
+ t)))
+ (unwind-protect
+ (progn ,@body)
+ ;; Unwind forms
+ (when fontlocked (font-lock-mode t))
+ (when hooked (verilog-run-hooks 'verilog-after-save-font-hook)))))
+
;;
;; Comment detection and caching
@@ -3161,7 +3221,7 @@
(defun verilog-insert (&rest stuff)
"Insert STUFF arguments, tracking for `verilog-inside-comment-or-string-p'.
-Any insert that includes a comment must have the entire commente
+Any insert that includes a comment must have the entire comment
inserted using a single call to `verilog-insert'."
(let ((pt (point)))
(while stuff
@@ -3565,9 +3625,10 @@
;; Stuff for GNU Emacs
(set (make-local-variable 'font-lock-defaults)
- `((verilog-font-lock-keywords verilog-font-lock-keywords-1
- verilog-font-lock-keywords-2
- verilog-font-lock-keywords-3)
+ `((verilog-font-lock-keywords
+ verilog-font-lock-keywords-1
+ verilog-font-lock-keywords-2
+ verilog-font-lock-keywords-3)
nil nil nil
,(if (functionp 'syntax-ppss)
;; verilog-beg-of-defun uses syntax-ppss, and syntax-ppss uses
@@ -4049,7 +4110,7 @@
(if (looking-at verilog-label-re)
(setq h (point))))
(goto-char h)))
- ;; stop if we see a complete reg, perhaps an extended one
+ ;; stop if we see an extended complete reg, perhaps a complete one
(and
(looking-at verilog-complete-reg)
(let* ((p (point)))
@@ -4186,32 +4247,20 @@
nil)))
(defun verilog-backward-up-list (arg)
- "Like `backward-up-list', but deal with comments."
+ "Call `backward-up-list' ARG, ignoring comments."
(let ((parse-sexp-ignore-comments t))
(backward-up-list arg)))
(defun verilog-forward-sexp-cmt (arg)
- "Call `forward-sexp', inside comments."
+ "Call `forward-sexp' ARG, inside comments."
(let ((parse-sexp-ignore-comments nil))
(forward-sexp arg)))
(defun verilog-forward-sexp-ign-cmt (arg)
- "Call `forward-sexp', ignoring comments."
+ "Call `forward-sexp' ARG, ignoring comments."
(let ((parse-sexp-ignore-comments t))
(forward-sexp arg)))
-(defun verilog-in-struct-region-p ()
- "Return true if in a struct region.
-More specifically, in a list after a struct|union keyword."
- (interactive)
- (save-excursion
- (let* ((state (verilog-syntax-ppss))
- (depth (nth 0 state)))
- (if depth
- (progn (verilog-backward-up-list depth)
- (verilog-beg-of-statement)
- (looking-at "\\<typedef\\>?\\s-*\\<struct\\|union\\>"))))))
-
(defun verilog-in-generate-region-p ()
"Return true if in a generate region.
More specifically, after a generate and before an endgenerate."
@@ -4658,10 +4707,10 @@
(cond
((match-end 5) ;; of verilog-end-block-ordered-re
(setq reg
"\\(\\<function\\>\\)\\|\\(\\<\\(endfunction\\|task\\|\\(macro\\)?module\\|primitive\\)\\>\\)")
- (setq name-re "\\w+\\s-*(")
- )
+ (setq name-re "\\w+\\s-*("))
((match-end 6) ;; of verilog-end-block-ordered-re
- (setq reg
"\\(\\<task\\>\\)\\|\\(\\<\\(endtask\\|function\\|\\(macro\\)?module\\|primitive\\)\\>\\)"))
+ (setq reg
"\\(\\<task\\>\\)\\|\\(\\<\\(endtask\\|function\\|\\(macro\\)?module\\|primitive\\)\\>\\)")
+ (setq name-re "\\w+\\s-*("))
((match-end 7) ;; of verilog-end-block-ordered-re
(setq reg
"\\(\\<\\(macro\\)?module\\>\\)\\|\\<endmodule\\>"))
((match-end 8) ;; of verilog-end-block-ordered-re
@@ -4977,25 +5026,24 @@
(compile compile-command))
(defun verilog-preprocess (&optional command filename)
- "Preprocess the buffer, similar to `compile', but leave output in
Verilog-Mode.
+ "Preprocess the buffer, similar to `compile', but put output in Verilog-Mode.
Takes optional COMMAND or defaults to `verilog-preprocessor', and
-FILENAME or defaults to `buffer-file-name`."
+FILENAME to find directory to run in, or defaults to `buffer-file-name`."
(interactive
(list
(let ((default (verilog-expand-command verilog-preprocessor)))
(set (make-local-variable `verilog-preprocessor)
- (read-from-minibuffer "Run Preprocessor (like this): "
- default nil nil
- 'verilog-preprocess-history default)))))
+ (read-from-minibuffer "Run Preprocessor (like this): "
+ default nil nil
+ 'verilog-preprocess-history default)))))
(unless command (setq command (verilog-expand-command verilog-preprocessor)))
(let* ((fontlocked (and (boundp 'font-lock-mode) font-lock-mode))
- (dir (file-name-directory (or filename buffer-file-name)))
- (file (file-name-nondirectory (or filename buffer-file-name)))
- (cmd (concat "cd " dir "; " command " " file)))
+ (dir (file-name-directory (or filename buffer-file-name)))
+ (cmd (concat "cd " dir "; " command)))
(with-output-to-temp-buffer "*Verilog-Preprocessed*"
(with-current-buffer (get-buffer "*Verilog-Preprocessed*")
(insert (concat "// " cmd "\n"))
- (shell-command cmd "*Verilog-Preprocessed*")
+ (call-process shell-file-name nil t nil shell-command-switch cmd)
(verilog-mode)
;; Without this force, it takes a few idle seconds
;; to get the color, which is very jarring
@@ -5006,17 +5054,30 @@
;; Batch
;;
+(defun verilog-warn (string &rest args)
+ "Print a warning with `format' using STRING and optional ARGS."
+ (apply 'message (concat "%%Warning: " string) args))
+
+(defun verilog-warn-error (string &rest args)
+ "Call `error' using STRING and optional ARGS.
+If `verilog-warn-fatal' is non-nil, call `verilog-warn' instead."
+ (if verilog-warn-fatal
+ (apply 'error string args)
+ (apply 'verilog-warn string args)))
+
(defmacro verilog-batch-error-wrapper (&rest body)
"Execute BODY and add error prefix to any errors found.
This lets programs calling batch mode to easily extract error messages."
- `(condition-case err
- (progn ,@body)
- (error
- (error "%%Error: %s%s" (error-message-string err)
- (if (featurep 'xemacs) "\n" ""))))) ;; XEmacs forgets to add a
newline
+ `(let ((verilog-warn-fatal nil))
+ (condition-case err
+ (progn ,@body)
+ (error
+ (error "%%Error: %s%s" (error-message-string err)
+ (if (featurep 'xemacs) "\n" "")))))) ;; XEmacs forgets to add a
newline
(defun verilog-batch-execute-func (funref &optional no-save)
- "Internal processing of a batch command, running FUNREF on all command
arguments.
+ "Internal processing of a batch command.
+Runs FUNREF on all command arguments.
Save the result unless optional NO-SAVE is t."
(verilog-batch-error-wrapper
;; Setting global variables like that is *VERY NASTY* !!! --Stef
@@ -5088,7 +5149,7 @@
(verilog-batch-execute-func `verilog-inject-auto))
(defun verilog-batch-indent ()
- "For use with --batch, reindent an a entire file as a stand-alone tool.
+ "For use with --batch, reindent an entire file as a stand-alone tool.
This sets up the appropriate Verilog mode environment, calls
\\[verilog-indent-buffer] on all command-line files, and saves the buffers."
(unless noninteractive
@@ -5219,7 +5280,7 @@
(verilog-beg-of-statement) ;; doesn't get to beginning
(if (looking-at verilog-property-re)
(throw 'nesting 'statement) ; We don't need an
endproperty for these
- (throw 'nesting 'block) ;We still need a
endproperty
+ (throw 'nesting 'block) ;We still need an
endproperty
))
(t ; endblock
; try to leap back to matching outward
block by striding across
@@ -5312,7 +5373,6 @@
(t
(setq depth (verilog-current-indent-level)))))
(message "You are at nesting %s depth %d" type depth))))
-
(defun verilog-calc-1 ()
(catch 'nesting
(let ((re (concat "\\({\\|}\\|" verilog-indent-re "\\)")))
@@ -5370,9 +5430,10 @@
; endfunction
(verilog-beg-of-statement)
(if (looking-at verilog-beg-block-re-ordered)
- (throw 'nesting 'block)
- (throw 'nesting 'defun)))
+ (throw 'nesting 'block)
+ (throw 'nesting 'defun)))
+ ;;
((looking-at "\\<property\\>")
; *sigh*
; {assert|assume|cover} property ();
are complete
@@ -5382,7 +5443,7 @@
(verilog-beg-of-statement)
(if (looking-at verilog-property-re)
(throw 'continue 'statement) ; We don't need an endproperty
for these
- (throw 'nesting 'block) ;We still need a endproperty
+ (throw 'nesting 'block) ;We still need an endproperty
))
(t (throw 'nesting 'block))))
@@ -5715,7 +5776,7 @@
(forward-comment (- (buffer-size))))
(defun verilog-backward-syntactic-ws-quick ()
- "As with `verilog-backward-syntactic-ws' but uses `verilog-scan' cache."
+ "As with `verilog-backward-syntactic-ws' but use `verilog-scan' cache."
(while (cond ((bobp)
nil) ; Done
((> (skip-syntax-backward " ") 0)
@@ -5864,7 +5925,7 @@
(defun verilog-in-paren-quick ()
"Return true if in a parenthetical expression.
-Always starts from point-min, to allow inserts with hooks disabled."
+Always starts from `point-min', to allow inserts with hooks disabled."
;; The -quick refers to its use alongside the other -quick functions,
;; not that it's likely to be faster than verilog-in-paren.
(let ((state (save-excursion (parse-partial-sexp (point-min) (point)))))
@@ -6118,7 +6179,7 @@
(indent-line-to val)
(if (and (not verilog-indent-lists)
(verilog-in-paren))
- (verilog-pretty-declarations))
+ (verilog-pretty-declarations-auto))
))
((= (preceding-char) ?\) )
(goto-char here)
@@ -6154,7 +6215,7 @@
(looking-at verilog-declaration-re))))
(indent-line-to val)
(if decl
- (verilog-pretty-declarations))))
+ (verilog-pretty-declarations-auto))))
(;-- Handle the ends
(or
@@ -6285,6 +6346,12 @@
;;
+(defun verilog-pretty-declarations-auto (&optional quiet)
+ "Call `verilog-pretty-declarations' QUIET based on `verilog-auto-lineup'."
+ (when (or (eq 'all verilog-auto-lineup)
+ (eq 'declarations verilog-auto-lineup))
+ (verilog-pretty-declarations quiet)))
+
(defun verilog-pretty-declarations (&optional quiet)
"Line up declarations around point.
Be verbose about progress unless optional QUIET set."
@@ -6431,100 +6498,101 @@
(interactive)
(if (not (verilog-in-comment-or-string-p))
(save-excursion
- (let ((rexp (concat "^\\s-*" verilog-complete-reg)))
- (beginning-of-line)
- (if (and (not (looking-at rexp ))
- (looking-at verilog-assignment-operation-re)
- (save-excursion
- (goto-char (match-end 2))
- (and (not (verilog-in-attribute-p))
- (not (verilog-in-parameter-p))
- (not (verilog-in-comment-or-string-p)))))
- (let* ((here (point))
- (e) (r)
- (start
- (progn
- (beginning-of-line)
- (setq e (point))
- (verilog-backward-syntactic-ws)
- (beginning-of-line)
- (while (and (not (looking-at rexp ))
- (looking-at verilog-assignment-operation-re)
- (not (bobp))
- )
- (setq e (point))
- (verilog-backward-syntactic-ws)
- (beginning-of-line)
- ) ;Ack, need to grok `define
- e))
- (end
- (progn
- (goto-char here)
- (end-of-line)
- (setq e (point)) ;Might be on last line
- (verilog-forward-syntactic-ws)
- (beginning-of-line)
- (while (and
- (not (looking-at rexp ))
- (looking-at verilog-assignment-operation-re)
- (progn
- (end-of-line)
- (not (eq e (point)))))
- (setq e (point))
- (verilog-forward-syntactic-ws)
- (beginning-of-line)
- )
- e))
- (endpos (set-marker (make-marker) end))
- (ind)
- )
- (goto-char start)
- (verilog-do-indent (verilog-calculate-indent))
- (if (and (not quiet)
- (> (- end start) 100))
- (message "Lining up expressions..(please stand by)"))
-
- ;; Set indent to minimum throughout region
- (while (< (point) (marker-position endpos))
- (beginning-of-line)
- (verilog-just-one-space verilog-assignment-operation-re)
- (beginning-of-line)
- (verilog-do-indent (verilog-calculate-indent))
- (end-of-line)
- (verilog-forward-syntactic-ws)
- )
-
- ;; Now find biggest prefix
- (setq ind (verilog-get-lineup-indent-2
verilog-assignment-operation-re start endpos))
-
- ;; Now indent each line.
- (goto-char start)
- (while (progn (setq e (marker-position endpos))
- (setq r (- e (point)))
- (> r 0))
- (setq e (point))
- (if (not quiet) (message "%d" r))
- (cond
- ((looking-at verilog-assignment-operation-re)
- (goto-char (match-beginning 2))
- (if (not (or (verilog-in-parenthesis-p) ;; leave attributes
and comparisons alone
- (verilog-in-coverage-p)))
- (if (eq (char-after) ?=)
- (indent-to (1+ ind)) ; line up the = of the
<= with surrounding =
- (indent-to ind)
- ))
- )
- ((verilog-continued-line-1 start)
- (goto-char e)
- (indent-line-to ind))
- (t ; Must be comment or white space
- (goto-char e)
- (verilog-forward-ws&directives)
- (forward-line -1))
- )
- (forward-line 1))
- (unless quiet (message ""))
- ))))))
+ (let ( (rexp (concat "^\\s-*" verilog-complete-reg))
+ (rexp1 (concat "^\\s-*" verilog-basic-complete-re)))
+ (beginning-of-line)
+ (if (and (not (looking-at rexp ))
+ (looking-at verilog-assignment-operation-re)
+ (save-excursion
+ (goto-char (match-end 2))
+ (and (not (verilog-in-attribute-p))
+ (not (verilog-in-parameter-p))
+ (not (verilog-in-comment-or-string-p)))))
+ (let* ((here (point))
+ (e) (r)
+ (start
+ (progn
+ (beginning-of-line)
+ (setq e (point))
+ (verilog-backward-syntactic-ws)
+ (beginning-of-line)
+ (while (and (not (looking-at rexp1))
+ (looking-at
verilog-assignment-operation-re)
+ (not (bobp))
+ )
+ (setq e (point))
+ (verilog-backward-syntactic-ws)
+ (beginning-of-line)
+ ) ;Ack, need to grok `define
+ e))
+ (end
+ (progn
+ (goto-char here)
+ (end-of-line)
+ (setq e (point)) ;Might be on last line
+ (verilog-forward-syntactic-ws)
+ (beginning-of-line)
+ (while (and
+ (not (looking-at rexp1 ))
+ (looking-at verilog-assignment-operation-re)
+ (progn
+ (end-of-line)
+ (not (eq e (point)))))
+ (setq e (point))
+ (verilog-forward-syntactic-ws)
+ (beginning-of-line)
+ )
+ e))
+ (endpos (set-marker (make-marker) end))
+ (ind)
+ )
+ (goto-char start)
+ (verilog-do-indent (verilog-calculate-indent))
+ (if (and (not quiet)
+ (> (- end start) 100))
+ (message "Lining up expressions..(please stand by)"))
+
+ ;; Set indent to minimum throughout region
+ (while (< (point) (marker-position endpos))
+ (beginning-of-line)
+ (verilog-just-one-space verilog-assignment-operation-re)
+ (beginning-of-line)
+ (verilog-do-indent (verilog-calculate-indent))
+ (end-of-line)
+ (verilog-forward-syntactic-ws)
+ )
+
+ ;; Now find biggest prefix
+ (setq ind (verilog-get-lineup-indent-2
verilog-assignment-operation-re start endpos))
+
+ ;; Now indent each line.
+ (goto-char start)
+ (while (progn (setq e (marker-position endpos))
+ (setq r (- e (point)))
+ (> r 0))
+ (setq e (point))
+ (if (not quiet) (message "%d" r))
+ (cond
+ ((looking-at verilog-assignment-operation-re)
+ (goto-char (match-beginning 2))
+ (if (not (or (verilog-in-parenthesis-p) ;; leave
attributes and comparisons alone
+ (verilog-in-coverage-p)))
+ (if (eq (char-after) ?=)
+ (indent-to (1+ ind)) ; line up the = of the
<= with surrounding =
+ (indent-to ind)
+ ))
+ )
+ ((verilog-continued-line-1 start)
+ (goto-char e)
+ (indent-line-to ind))
+ (t ; Must be comment or white space
+ (goto-char e)
+ (verilog-forward-ws&directives)
+ (forward-line -1))
+ )
+ (forward-line 1))
+ (unless quiet (message ""))
+ ))))))
(defun verilog-just-one-space (myre)
"Remove extra spaces around regular expression MYRE."
@@ -7365,6 +7433,7 @@
;;
;; Elements of a signal list
+;; Unfortunately we use 'assoc' on this, so can't be a vector
(defsubst verilog-sig-new (name bits comment mem enum signed type multidim
modport)
(list name bits comment mem enum signed type multidim modport))
(defsubst verilog-sig-name (sig)
@@ -7381,6 +7450,8 @@
(nth 5 sig))
(defsubst verilog-sig-type (sig)
(nth 6 sig))
+(defsubst verilog-sig-type-set (sig type)
+ (setcar (nthcdr 6 sig) type))
(defsubst verilog-sig-multidim (sig)
(nth 7 sig))
(defsubst verilog-sig-multidim-string (sig)
@@ -7396,17 +7467,17 @@
(verilog-make-width-expression (verilog-sig-bits sig)))
(defsubst verilog-alw-new (outputs-del outputs-imm temps inputs)
- (list outputs-del outputs-imm temps inputs))
+ (vector outputs-del outputs-imm temps inputs))
(defsubst verilog-alw-get-outputs-delayed (sigs)
- (nth 0 sigs))
+ (aref sigs 0))
(defsubst verilog-alw-get-outputs-immediate (sigs)
- (nth 1 sigs))
+ (aref sigs 1))
(defsubst verilog-alw-get-temps (sigs)
- (nth 2 sigs))
+ (aref sigs 2))
(defsubst verilog-alw-get-inputs (sigs)
- (nth 3 sigs))
+ (aref sigs 3))
(defsubst verilog-alw-get-uses-delayed (sigs)
- (nth 0 sigs))
+ (aref sigs 0))
(defsubst verilog-modi-new (name fob pt type)
(vector name fob pt type))
@@ -7459,6 +7530,11 @@
(defsubst verilog-subdecls-get-interfaced (subdecls)
(aref subdecls 4))
+(defun verilog-signals-from-signame (signame-list)
+ "Return signals in standard form from SIGNAME-LIST, a simple list of names."
+ (mapcar (lambda (name) (verilog-sig-new name nil nil nil nil nil nil nil
nil))
+ signame-list))
+
(defun verilog-signals-not-in (in-list not-list)
"Return list of signals in IN-LIST that aren't also in NOT-LIST.
Also remove any duplicates in IN-LIST.
@@ -7471,17 +7547,17 @@
(puthash (car (car not-list)) t ht)
(setq not-list (cdr not-list)))
(while in-list
- (when (not (gethash (car (car in-list)) ht))
+ (when (not (gethash (verilog-sig-name (car in-list)) ht))
(setq out-list (cons (car in-list) out-list))
- (puthash (car (car in-list)) t ht))
+ (puthash (verilog-sig-name (car in-list)) t ht))
(setq in-list (cdr in-list)))
(nreverse out-list)))
;; Slower Fallback if no hash tables (pre Emacs 21.1/XEmacs 21.4)
(t
(let (out-list)
(while in-list
- (if (not (or (assoc (car (car in-list)) not-list)
- (assoc (car (car in-list)) out-list)))
+ (if (not (or (assoc (verilog-sig-name (car in-list)) not-list)
+ (assoc (verilog-sig-name (car in-list)) out-list)))
(setq out-list (cons (car in-list) out-list)))
(setq in-list (cdr in-list)))
(nreverse out-list)))))
@@ -7499,13 +7575,22 @@
(defun verilog-signals-sort-compare (a b)
"Compare signal A and B for sorting."
- (string< (car a) (car b)))
+ (string< (verilog-sig-name a) (verilog-sig-name b)))
(defun verilog-signals-not-params (in-list)
"Return list of signals in IN-LIST that aren't parameters or numeric
constants."
(let (out-list)
(while in-list
- (unless (boundp (intern (concat "vh-" (car (car in-list)))))
+ (unless (boundp (intern (concat "vh-" (verilog-sig-name (car in-list)))))
+ (setq out-list (cons (car in-list) out-list)))
+ (setq in-list (cdr in-list)))
+ (nreverse out-list)))
+
+(defun verilog-signals-with (func in-list)
+ "Return IN-LIST with only signals where FUNC passed each signal is true."
+ (let (out-list)
+ (while in-list
+ (when (funcall func (car in-list))
(setq out-list (cons (car in-list) out-list)))
(setq in-list (cdr in-list)))
(nreverse out-list)))
@@ -7594,20 +7679,67 @@
;;
out-list))
-(defun verilog-sig-tieoff (sig &optional no-width)
+(defun verilog-sig-tieoff (sig)
"Return tieoff expression for given SIG, with appropriate width.
-Ignore width if optional NO-WIDTH is set."
- (let* ((width (if no-width nil (verilog-sig-width sig))))
- (concat
- (if (and verilog-active-low-regexp
- (string-match verilog-active-low-regexp (verilog-sig-name sig)))
- "~" "")
- (cond ((not width)
- "0")
- ((string-match "^[0-9]+$" width)
- (concat width (if (verilog-sig-signed sig) "'sh0" "'h0")))
- (t
- (concat "{" width "{1'b0}}"))))))
+Tieoff value uses `verilog-active-low-regexp' and
+`verilog-auto-reset-widths'."
+ (concat
+ (if (and verilog-active-low-regexp
+ (string-match verilog-active-low-regexp (verilog-sig-name sig)))
+ "~" "")
+ (cond ((not verilog-auto-reset-widths)
+ "0")
+ ((equal verilog-auto-reset-widths 'unbased)
+ "'0")
+ ;; Else presume verilog-auto-reset-widths is true
+ (t
+ (let* ((width (verilog-sig-width sig)))
+ (if (string-match "^[0-9]+$" width)
+ (concat width (if (verilog-sig-signed sig) "'sh0" "'h0"))
+ (concat "{" width "{1'b0}}")))))))
+
+;;
+;; Dumping
+;;
+
+(defun verilog-decls-princ (decls)
+ "For debug, dump the `verilog-read-decls' structure DECLS."
+ (verilog-signals-princ (verilog-decls-get-outputs decls)
+ "Outputs:\n" " ")
+ (verilog-signals-princ (verilog-decls-get-inouts decls)
+ "Inout:\n" " ")
+ (verilog-signals-princ (verilog-decls-get-inputs decls)
+ "Inputs:\n" " ")
+ (verilog-signals-princ (verilog-decls-get-vars decls)
+ "Vars:\n" " ")
+ (verilog-signals-princ (verilog-decls-get-assigns decls)
+ "Assigns:\n" " ")
+ (verilog-signals-princ (verilog-decls-get-consts decls)
+ "Consts:\n" " ")
+ (verilog-signals-princ (verilog-decls-get-gparams decls)
+ "Gparams:\n" " ")
+ (verilog-signals-princ (verilog-decls-get-interfaces decls)
+ "Interfaces:\n" " ")
+ (princ "\n"))
+
+(defun verilog-signals-princ (signals &optional header prefix)
+ "For debug, dump internal SIGNALS structures, with HEADER and PREFIX."
+ (when signals
+ (princ header)
+ (while signals
+ (let ((sig (car signals)))
+ (setq signals (cdr signals))
+ (princ prefix)
+ (princ "\"") (princ (verilog-sig-name sig)) (princ "\"")
+ (princ " bits=") (princ (verilog-sig-bits sig))
+ (princ " cmt=") (princ (verilog-sig-comment sig))
+ (princ " mem=") (princ (verilog-sig-memory sig))
+ (princ " enum=") (princ (verilog-sig-enum sig))
+ (princ " sign=") (princ (verilog-sig-signed sig))
+ (princ " type=") (princ (verilog-sig-type sig))
+ (princ " dim=") (princ (verilog-sig-multidim sig))
+ (princ " modp=") (princ (verilog-sig-modport sig))
+ (princ "\n")))))
;;
;; Port/Wire/Etc Reading
@@ -7701,7 +7833,7 @@
(let ((olist))
(save-excursion
;; /*AUTOPUNT("parameter", "parameter")*/
- (search-backward "(")
+ (backward-sexp 1)
(while (looking-at "(?\\s *\"\\([^\"]*\\)\"\\s *,?")
(setq olist (cons (match-string 1) olist))
(goto-char (match-end 0))))
@@ -7716,10 +7848,10 @@
(defun verilog-read-decls ()
"Compute signal declaration information for the current module at point.
-Return a array of [outputs inouts inputs wire reg assign const]."
+Return an array of [outputs inouts inputs wire reg assign const]."
(let ((end-mod-point (or (verilog-get-end-of-defun t) (point-max)))
(functask 0) (paren 0) (sig-paren 0) (v2kargs-ok t)
- in-modport ign-prop
+ in-modport ptype ign-prop
sigs-in sigs-out sigs-inout sigs-var sigs-assign sigs-const
sigs-gparam sigs-intf
vec expect-signal keywd newsig rvalue enum io signed typedefed multidim
@@ -7731,13 +7863,13 @@
;;(if dbg (setq dbg (concat dbg (format "Pt %s Vec %s C%c Kwd'%s'\n"
(point) vec (following-char) keywd))))
(cond
((looking-at "//")
- (if (looking-at "[^\n]*synopsys\\s +enum\\s +\\([a-zA-Z0-9_]+\\)")
- (setq enum (match-string 1)))
+ (if (looking-at "[^\n]*\\(auto\\|synopsys\\)\\s +enum\\s
+\\([a-zA-Z0-9_]+\\)")
+ (setq enum (match-string 2)))
(search-forward "\n"))
((looking-at "/\\*")
(forward-char 2)
- (if (looking-at "[^\n]*synopsys\\s +enum\\s +\\([a-zA-Z0-9_]+\\)")
- (setq enum (match-string 1)))
+ (if (looking-at "[^\n]*\\(auto\\|synopsys\\)\\s +enum\\s
+\\([a-zA-Z0-9_]+\\)")
+ (setq enum (match-string 2)))
(or (search-forward "*/")
(error "%s: Unmatched /* */, at char %d" (verilog-point-text)
(point))))
((looking-at "(\\*")
@@ -7795,33 +7927,49 @@
(when (string-match "^\\\\" (match-string 1))
(setq keywd (concat keywd " ")))) ;; Escaped ID needs space at
end
(cond ((equal keywd "input")
- (setq vec nil enum nil rvalue nil newsig nil signed nil
typedefed nil multidim nil sig-paren paren
- expect-signal 'sigs-in io t modport nil))
+ (setq vec nil enum nil rvalue nil newsig nil
signed nil
+ typedefed nil multidim nil ptype nil modport nil
+ expect-signal 'sigs-in io t sig-paren
paren))
((equal keywd "output")
- (setq vec nil enum nil rvalue nil newsig nil signed nil
typedefed nil multidim nil sig-paren paren
- expect-signal 'sigs-out io t modport nil))
+ (setq vec nil enum nil rvalue nil newsig nil
signed nil
+ typedefed nil multidim nil ptype nil modport nil
+ expect-signal 'sigs-out io t sig-paren
paren))
((equal keywd "inout")
- (setq vec nil enum nil rvalue nil newsig nil signed nil
typedefed nil multidim nil sig-paren paren
- expect-signal 'sigs-inout io t modport nil))
+ (setq vec nil enum nil rvalue nil newsig nil
signed nil
+ typedefed nil multidim nil ptype nil modport nil
+ expect-signal 'sigs-inout io t sig-paren
paren))
((equal keywd "parameter")
- (setq vec nil enum nil rvalue nil signed nil typedefed nil
multidim nil sig-paren paren
- expect-signal 'sigs-gparam io t modport nil))
- ((member keywd '("wire"
- "tri" "tri0" "tri1" "triand" "trior" "wand"
"wor"
- "reg" "trireg"
+ (setq vec nil enum nil rvalue nil signed nil
+ typedefed nil multidim nil ptype nil modport nil
+ expect-signal 'sigs-gparam io t sig-paren
paren))
+ ((member keywd '("wire" "reg" ; Fast
+ ;; net_type
+ "tri" "tri0" "tri1" "triand" "trior" "trireg"
+ "uwire" "wand" "wor"
+ ;; integer_atom_type
"byte" "shortint" "int" "longint" "integer"
"time"
+ "supply0" "supply1"
+ ;; integer_vector_type - "reg" above
"bit" "logic"
+ ;; non_integer_type
"shortreal" "real" "realtime"
+ ;; data_type
"string" "event" "chandle"))
- (unless io (setq vec nil enum nil rvalue nil signed nil
typedefed nil multidim nil sig-paren paren
- expect-signal 'sigs-var modport nil)))
+ (cond (io
+ (setq typedefed
+ (if typedefed (concat typedefed " " keywd)
keywd)))
+ (t (setq vec nil enum nil rvalue nil signed nil
+ typedefed nil multidim nil sig-paren paren
+ expect-signal 'sigs-var modport nil))))
((equal keywd "assign")
- (setq vec nil enum nil rvalue nil signed nil typedefed nil
multidim nil sig-paren paren
- expect-signal 'sigs-assign modport nil))
- ((member keywd '("supply0" "supply1" "supply"
- "localparam" "genvar"))
- (unless io (setq vec nil enum nil rvalue nil signed nil
typedefed nil multidim nil sig-paren paren
- expect-signal 'sigs-const modport nil)))
+ (setq vec nil enum nil rvalue nil signed nil
+ typedefed nil multidim nil ptype nil modport nil
+ expect-signal 'sigs-assign sig-paren paren))
+ ((member keywd '("localparam" "genvar"))
+ (unless io
+ (setq vec nil enum nil rvalue nil signed nil
+ typedefed nil multidim nil ptype nil modport nil
+ expect-signal 'sigs-const sig-paren paren)))
((member keywd '("signed" "unsigned"))
(setq signed keywd))
((member keywd '("assert" "assume" "cover" "expect" "restrict"))
@@ -7835,11 +7983,14 @@
(setq functask (1- functask)))
((equal keywd "modport")
(setq in-modport t))
+ ((equal keywd "type")
+ (setq ptype t))
;; Ifdef? Ignore name of define
((member keywd '("`ifdef" "`ifndef" "`elsif"))
(setq rvalue t))
;; Type?
- ((verilog-typedef-name-p keywd)
+ ((unless ptype
+ (verilog-typedef-name-p keywd))
(setq typedefed keywd))
;; Interface with optional modport in v2k arglist?
;; Skip over parsing modport, and take the interface name as
the type
@@ -7848,8 +7999,10 @@
(not rvalue)
(looking-at
"\\s-*\\(\\.\\(\\s-*[a-zA-Z`_$][a-zA-Z0-9`_$]*\\)\\|\\)\\s-*[a-zA-Z`_$][a-zA-Z0-9`_$]*"))
(when (match-end 2) (goto-char (match-end 2)))
- (setq vec nil enum nil rvalue nil newsig nil signed nil
typedefed keywd multidim nil sig-paren paren
- expect-signal 'sigs-intf io t modport (match-string
2)))
+ (setq vec nil enum nil rvalue nil signed nil
+ typedefed keywd multidim nil ptype nil modport
(match-string 2)
+ newsig nil sig-paren paren
+ expect-signal 'sigs-intf io t ))
;; Ignore dotted LHS assignments: "assign foo.bar = z;"
((looking-at "\\s-*\\.")
(goto-char (match-end 0))
@@ -7888,7 +8041,7 @@
(eval-when-compile
;; Prevent compile warnings; these are let's, not globals
;; Do not remove the eval-when-compile
- ;; - we want a error when we are debugging this code if they are refed.
+ ;; - we want an error when we are debugging this code if they are refed.
(defvar sigs-in)
(defvar sigs-inout)
(defvar sigs-out)
@@ -7918,7 +8071,8 @@
(verilog-sig-memory portdata)
nil
(verilog-sig-signed portdata)
- (verilog-sig-type portdata)
+ (unless (member (verilog-sig-type portdata)
'("wire" "reg"))
+ (verilog-sig-type portdata))
multidim nil)
sigs-inout)))
((or (setq portdata (assoc port (verilog-decls-get-outputs
submoddecls)))
@@ -7931,7 +8085,13 @@
(verilog-sig-memory portdata)
nil
(verilog-sig-signed portdata)
- (verilog-sig-type portdata)
+ ;; Though ok in SV, in V2K code, propagating the
+ ;; "reg" in "output reg" upwards isn't legal.
+ ;; Also for backwards compatibility we don't
propagate
+ ;; "input wire" upwards.
+ ;; See also `verilog-signals-edit-wire-reg'.
+ (unless (member (verilog-sig-type portdata)
'("wire" "reg"))
+ (verilog-sig-type portdata))
multidim nil)
sigs-out)))
((or (setq portdata (assoc port (verilog-decls-get-inputs
submoddecls)))
@@ -7944,7 +8104,8 @@
(verilog-sig-memory portdata)
nil
(verilog-sig-signed portdata)
- (verilog-sig-type portdata)
+ (unless (member (verilog-sig-type portdata)
'("wire" "reg"))
+ (verilog-sig-type portdata))
multidim nil)
sigs-in)))
((setq portdata (assoc port (verilog-decls-get-interfaces
submoddecls)))
@@ -8110,9 +8271,9 @@
(defun verilog-read-sub-decls ()
"Internally parse signals going to modules under this module.
-Return a array of [ outputs inouts inputs ] signals for modules that are
+Return an array of [ outputs inouts inputs ] signals for modules that are
instantiated in this module. For example if declare A A (.B(SIG)) and SIG
-is a output, then SIG will be included in the list.
+is an output, then SIG will be included in the list.
This only works on instantiations created with /*AUTOINST*/ converted by
\\[verilog-auto-inst]. Otherwise, it would have to read in the whole
@@ -8245,7 +8406,7 @@
(setq verilog-cache-has-lisp (re-search-forward "\\<AUTO_LISP(" nil t))))
(defun verilog-read-auto-lisp (start end)
- "Look for and evaluate a AUTO_LISP between START and END.
+ "Look for and evaluate an AUTO_LISP between START and END.
Must call `verilog-read-auto-lisp-present' before this function."
;; This function is expensive for large buffers, so we cache if any
AUTO_LISP exists
(when verilog-cache-has-lisp
@@ -8255,13 +8416,14 @@
(backward-char)
(let* ((beg-pt (prog1 (point)
(verilog-forward-sexp-cmt 1))) ;; Closing paren
- (end-pt (point)))
+ (end-pt (point))
+ (verilog-in-hooks t))
(eval-region beg-pt end-pt nil))))))
(eval-when-compile
;; Prevent compile warnings; these are let's, not globals
;; Do not remove the eval-when-compile
- ;; - we want a error when we are debugging this code if they are refed.
+ ;; - we want an error when we are debugging this code if they are refed.
(defvar sigs-in)
(defvar sigs-out-d)
(defvar sigs-out-i)
@@ -8455,17 +8617,89 @@
instants-list))
-(defun verilog-read-auto-template (module)
- "Look for a auto_template for the instantiation of the given MODULE.
-If found returns the signal name connections. Return REGEXP and
-list of ( (signal_name connection_name)... )."
+(defun verilog-read-auto-template-middle ()
+ "With point in middle of an AUTO_TEMPLATE, parse it.
+Returns REGEXP and list of ( (signal_name connection_name)... )."
(save-excursion
;; Find beginning
(let ((tpl-regexp "\\([0-9]+\\)")
(lineno -1) ; -1 to offset for the AUTO_TEMPLATE's newline
(templateno 0)
- (pt (point))
tpl-sig-list tpl-wild-list tpl-end-pt rep)
+ ;; Parse "REGEXP"
+ ;; We reserve @"..." for future lisp expressions that evaluate
+ ;; once-per-AUTOINST
+ (when (looking-at "\\s-*\"\\([^\"]*\\)\"")
+ (setq tpl-regexp (match-string 1))
+ (goto-char (match-end 0)))
+ (search-forward "(")
+ ;; Parse lines in the template
+ (when (or verilog-auto-inst-template-numbers
+ verilog-auto-template-warn-unused)
+ (save-excursion
+ (let ((pre-pt (point)))
+ (goto-char (point-min))
+ (while (search-forward "AUTO_TEMPLATE" pre-pt t)
+ (setq templateno (1+ templateno)))
+ (while (< (point) pre-pt)
+ (forward-line 1)
+ (setq lineno (1+ lineno))))))
+ (setq tpl-end-pt (save-excursion
+ (backward-char 1)
+ (verilog-forward-sexp-cmt 1) ;; Moves to paren that
closes argdecl's
+ (backward-char 1)
+ (point)))
+ ;;
+ (while (< (point) tpl-end-pt)
+ (cond ((looking-at
"\\s-*\\.\\([a-zA-Z0-9`_$]+\\)\\s-*(\\(.*\\))\\s-*\\(,\\|)\\s-*;\\)")
+ (setq tpl-sig-list
+ (cons (list
+ (match-string-no-properties 1)
+ (match-string-no-properties 2)
+ templateno lineno)
+ tpl-sig-list))
+ (goto-char (match-end 0)))
+ ;; Regexp form??
+ ((looking-at
+ ;; Regexp bug in XEmacs disallows ][ inside [], and wants + last
+
"\\s-*\\.\\(\\(address@hidden|---]+\\|[][]\\|\\\\[()|]\\)+\\)\\s-*(\\(.*\\))\\s-*\\(,\\|)\\s-*;\\)")
+ (setq rep (match-string-no-properties 3))
+ (goto-char (match-end 0))
+ (setq tpl-wild-list
+ (cons (list
+ (concat "^"
+ (verilog-string-replace-matches "@"
"\\\\([0-9]+\\\\)" nil nil
+
(match-string 1))
+ "$")
+ rep
+ templateno lineno)
+ tpl-wild-list)))
+ ((looking-at "[ \t\f]+")
+ (goto-char (match-end 0)))
+ ((looking-at "\n")
+ (setq lineno (1+ lineno))
+ (goto-char (match-end 0)))
+ ((looking-at "//")
+ (search-forward "\n")
+ (setq lineno (1+ lineno)))
+ ((looking-at "/\\*")
+ (forward-char 2)
+ (or (search-forward "*/")
+ (error "%s: Unmatched /* */, at char %d"
(verilog-point-text) (point))))
+ (t
+ (error "%s: AUTO_TEMPLATE parsing error: %s"
+ (verilog-point-text)
+ (progn (looking-at ".*$") (match-string 0))))))
+ ;; Return
+ (vector tpl-regexp
+ (list tpl-sig-list tpl-wild-list)))))
+
+(defun verilog-read-auto-template (module)
+ "Look for an auto_template for the instantiation of the given MODULE.
+If found returns `verilog-read-auto-template-inside' structure."
+ (save-excursion
+ ;; Find beginning
+ (let ((pt (point)))
;; Note this search is expensive, as we hunt from mod-begin to point
;; for every instantiation. Likewise in verilog-read-auto-lisp.
;; So, we look first for an exact string rather than a slow regexp.
@@ -8473,6 +8707,7 @@
;; need to record the relative position of each AUTOINST, as multiple
;; templates exist for each module, and we're inserting lines.
(cond ((or
+ ;; See also regexp in `verilog-auto-template-lint'
(verilog-re-search-backward-substr
"AUTO_TEMPLATE"
(concat "^\\s-*/?\\*?\\s-*" module "\\s-+AUTO_TEMPLATE") nil t)
@@ -8484,76 +8719,24 @@
"AUTO_TEMPLATE"
(concat "^\\s-*/?\\*?\\s-*" module "\\s-+AUTO_TEMPLATE") nil
t)))
(goto-char (match-end 0))
- ;; Parse "REGEXP"
- ;; We reserve @"..." for future lisp expressions that evaluate
- ;; once-per-AUTOINST
- (when (looking-at "\\s-*\"\\([^\"]*\\)\"")
- (setq tpl-regexp (match-string 1))
- (goto-char (match-end 0)))
- (search-forward "(")
- ;; Parse lines in the template
- (when verilog-auto-inst-template-numbers
- (save-excursion
- (let ((pre-pt (point)))
- (goto-char (point-min))
- (while (search-forward "AUTO_TEMPLATE" pre-pt t)
- (setq templateno (1+ templateno)))
- (while (< (point) pre-pt)
- (forward-line 1)
- (setq lineno (1+ lineno))))))
- (setq tpl-end-pt (save-excursion
- (backward-char 1)
- (verilog-forward-sexp-cmt 1) ;; Moves to
paren that closes argdecl's
- (backward-char 1)
- (point)))
- ;;
- (while (< (point) tpl-end-pt)
- (cond ((looking-at
"\\s-*\\.\\([a-zA-Z0-9`_$]+\\)\\s-*(\\(.*\\))\\s-*\\(,\\|)\\s-*;\\)")
- (setq tpl-sig-list
- (cons (list
- (match-string-no-properties 1)
- (match-string-no-properties 2)
- templateno lineno)
- tpl-sig-list))
- (goto-char (match-end 0)))
- ;; Regexp form??
- ((looking-at
- ;; Regexp bug in XEmacs disallows ][ inside [], and
wants + last
-
"\\s-*\\.\\(\\(address@hidden|---]+\\|[][]\\|\\\\[()|]\\)+\\)\\s-*(\\(.*\\))\\s-*\\(,\\|)\\s-*;\\)")
- (setq rep (match-string-no-properties 3))
- (goto-char (match-end 0))
- (setq tpl-wild-list
- (cons (list
- (concat "^"
- (verilog-string-replace-matches "@"
"\\\\([0-9]+\\\\)" nil nil
-
(match-string 1))
- "$")
- rep
- templateno lineno)
- tpl-wild-list)))
- ((looking-at "[ \t\f]+")
- (goto-char (match-end 0)))
- ((looking-at "\n")
- (setq lineno (1+ lineno))
- (goto-char (match-end 0)))
- ((looking-at "//")
- (search-forward "\n")
- (setq lineno (1+ lineno)))
- ((looking-at "/\\*")
- (forward-char 2)
- (or (search-forward "*/")
- (error "%s: Unmatched /* */, at char %d"
(verilog-point-text) (point))))
- (t
- (error "%s: AUTO_TEMPLATE parsing error: %s"
- (verilog-point-text)
- (progn (looking-at ".*$") (match-string 0))))))
- ;; Return
- (vector tpl-regexp
- (list tpl-sig-list tpl-wild-list)))
+ (verilog-read-auto-template-middle))
;; If no template found
- (t (vector tpl-regexp nil))))))
+ (t (vector "" nil))))))
;;(progn (find-file "auto-template.v") (verilog-read-auto-template
"ptl_entry"))
+(defvar verilog-auto-template-hits nil "Successful lookups with
`verilog-read-auto-template-hit'.")
+(make-variable-buffer-local 'verilog-auto-template-hits)
+
+(defun verilog-read-auto-template-hit (tpl-ass)
+ "Record that TPL-ASS template from `verilog-read-auto-template' was used."
+ (when (eval-when-compile (fboundp 'make-hash-table)) ;; else feature not
allowed
+ (when verilog-auto-template-warn-unused
+ (unless verilog-auto-template-hits
+ (setq verilog-auto-template-hits
+ (make-hash-table :test 'equal :rehash-size 4.0)))
+ (puthash (vector (nth 2 tpl-ass) (nth 3 tpl-ass)) t
+ verilog-auto-template-hits))))
+
(defun verilog-set-define (defname defvalue &optional buffer enumname)
"Set the definition DEFNAME to the DEFVALUE in the given BUFFER.
Optionally associate it with the specified enumeration ENUMNAME."
@@ -8642,15 +8825,15 @@
(let (enumname)
;; The primary way of getting defines is verilog-read-decls
;; However, that isn't called yet for included files, so we'll add
another scheme
- (if (looking-at "[^\n]*synopsys\\s +enum\\s +\\([a-zA-Z0-9_]+\\)")
- (setq enumname (match-string-no-properties 1)))
- (forward-comment 999)
+ (if (looking-at "[^\n]*\\(auto\\|synopsys\\)\\s +enum\\s
+\\([a-zA-Z0-9_]+\\)")
+ (setq enumname (match-string-no-properties 2)))
+ (forward-comment 99999)
(while (looking-at (concat
"\\s-*,?\\s-*\\(?:/[/*].*?$\\)?\\s-*\\([a-zA-Z0-9_$]+\\)"
"\\s-*=\\s-*\\([^;,]*\\),?\\s-*\\(/[/*].*?$\\)?\\s-*"))
(verilog-set-define (match-string-no-properties 1)
(match-string-no-properties 2) origbuf enumname)
(goto-char (match-end 0))
- (forward-comment 999)))))))
+ (forward-comment 99999)))))))
(defun verilog-read-includes ()
"Read `includes for the current file.
@@ -8675,7 +8858,7 @@
variable over and over when many modules are compiled together, put a test
around the inside each include file:
-foo.v (a include):
+foo.v (an include file):
`ifdef _FOO_V // include if not already included
`else
`define _FOO_V
@@ -9038,7 +9221,7 @@
(defun verilog-library-filenames (filename &optional current check-ext)
"Return a search path to find the given FILENAME or module name.
-Uses the optional CURRENT filename or buffer-file-name, plus
+Uses the optional CURRENT filename or variable `buffer-file-name', plus
`verilog-library-directories' and `verilog-library-extensions'
variables to build the path. With optional CHECK-EXT also check
`verilog-library-extensions'."
@@ -9091,7 +9274,7 @@
;; A modi is: [module-name-string file-name begin-point]
(defvar verilog-cache-enabled t
- "If true, enable caching of signals, etc. Set to nil for debugging to make
things SLOW!")
+ "Non-nil enables caching of signals, etc. Set to nil for debugging to make
things SLOW!")
(defvar verilog-modi-cache-list nil
"Cache of ((Module Function) Buf-Tick Buf-Modtime Func-Returns)...
@@ -9106,7 +9289,7 @@
"Modification tick after which the cache is still considered valid.
Use `verilog-preserve-modi-cache' to set it.")
(defvar verilog-modi-cache-current-enable nil
- "If true, allow caching `verilog-modi-current', set by let().")
+ "Non-nil means allow caching `verilog-modi-current', set by let().")
(defvar verilog-modi-cache-current nil
"Currently active `verilog-modi-current', if any, set by let().")
(defvar verilog-modi-cache-current-max nil
@@ -9245,13 +9428,9 @@
(t
;; Read from file
;; Clear then restore any highlighting to make emacs19 happy
- (let ((fontlocked (when (and (boundp 'font-lock-mode)
- font-lock-mode)
- (font-lock-mode 0)
- t))
- func-returns)
- (setq func-returns (funcall function))
- (when fontlocked (font-lock-mode t))
+ (let (func-returns)
+ (verilog-save-font-mods
+ (setq func-returns (funcall function)))
;; Cache for next time
(setq verilog-modi-cache-list
(cons (list (list modi function)
@@ -9341,9 +9520,16 @@
(setq in-list (cdr in-list)))
(nreverse out-list))))
+(defun verilog-signals-edit-wire-reg (in-list)
+ "Return all signals in IN-LIST with wire/reg data types made blank."
+ (mapcar (lambda (sig)
+ (when (member (verilog-sig-type sig) '("wire" "reg"))
+ (verilog-sig-type-set sig nil))
+ sig) in-list))
+
;; Combined
(defun verilog-decls-get-signals (decls)
- "Return all declared signals, excluding 'assign' statements."
+ "Return all declared signals in DECLS, excluding 'assign' statements."
(append
(verilog-decls-get-outputs decls)
(verilog-decls-get-inouts decls)
@@ -9367,10 +9553,6 @@
(defsubst verilog-modi-cache-add-vars (modi sig-list)
(verilog-modi-cache-add modi 'verilog-read-decls 3 sig-list))
-(defun verilog-signals-from-signame (signame-list)
- "Return signals in standard form from SIGNAME-LIST, a simple list of signal
names."
- (mapcar (function (lambda (name) (list name nil nil)))
- signame-list))
;;
;; Auto creation utilities
@@ -9473,7 +9655,7 @@
;;(let ((indent-pt 10)) (verilog-insert-indent "hello\n" "addon" "there\n"))
(defun verilog-repair-open-comma ()
- "Insert comma if previous argument is other than a open parenthesis or
endif."
+ "Insert comma if previous argument is other than an open parenthesis or
endif."
;; We can't just search backward for ) as it might be inside another
expression.
;; Also want "`ifdef X input foo `endif" to just leave things to the
human to deal with
(save-excursion
@@ -9489,7 +9671,7 @@
(defun verilog-repair-close-comma ()
"If point is at a comma followed by a close parenthesis, fix it.
-This repairs those mis-inserted by a AUTOARG."
+This repairs those mis-inserted by an AUTOARG."
;; It would be much nicer if Verilog allowed extra commas like Perl does!
(save-excursion
(verilog-forward-close-paren)
@@ -9974,15 +10156,16 @@
Differences are between buffers B1 and B2, starting at point
DIFFPT. This function is called via `verilog-diff-function'."
(let ((name1 (with-current-buffer b1 (buffer-file-name))))
- (message "%%Warning: %s:%d: Difference in AUTO expansion found"
- name1 (with-current-buffer b1 (1+ (count-lines (point-min)
(point)))))
+ (verilog-warn "%s:%d: Difference in AUTO expansion found"
+ name1 (with-current-buffer b1
+ (1+ (count-lines (point-min) (point)))))
(cond (noninteractive
(verilog-diff-file-with-buffer name1 b2 t t))
(t
(ediff-buffers b1 b2)))))
(defun verilog-diff-auto ()
- "Expand AUTOs in a temporary buffer and indicate any changes.
+ "Expand AUTOs in a temporary buffer and indicate any change.
Whitespace differences are ignored to determine identicalness, but
once a difference is detected, whitespace differences may be shown.
@@ -10076,7 +10259,7 @@
;;
(defun verilog-auto-arg-ports (sigs message indent-pt)
- "Print a list of ports for a AUTOINST.
+ "Print a list of ports for an AUTOINST.
Takes SIGS list, adds MESSAGE to front and inserts each at INDENT-PT."
(when sigs
(when verilog-auto-arg-sort
@@ -10178,7 +10361,7 @@
(defvar vl-mbits nil "See `verilog-auto-inst'.") ; Prevent compile warning
(defun verilog-auto-inst-port (port-st indent-pt tpl-list tpl-num for-star
par-values)
- "Print out a instantiation connection for this PORT-ST.
+ "Print out an instantiation connection for this PORT-ST.
Insert to INDENT-PT, use template TPL-LIST.
@ are instantiation numbers, replaced with TPL-NUM.
@\"(expression @)\" are evaluated, with @ as a variable.
@@ -10266,6 +10449,7 @@
(insert "(" tpl-net ")"))
(insert ",")
(cond (tpl-ass
+ (verilog-read-auto-template-hit tpl-ass)
(indent-to (+ (if (< verilog-auto-inst-column 48) 24 16)
verilog-auto-inst-column))
;; verilog-insert requires the complete comment in one call -
including the newline
@@ -10302,7 +10486,7 @@
(defun verilog-auto-inst-first ()
"Insert , etc before first ever port in this instant, as part of
\\[verilog-auto-inst]."
;; Do we need a trailing comma?
- ;; There maybe a ifdef or something similar before us. What a mess. Thus
+ ;; There maybe an ifdef or something similar before us. What a mess. Thus
;; to avoid trouble we only insert on preceding ) or *.
;; Insert first port on new line
(insert "\n") ;; Must insert before search, so point will move forward if
insert comma
@@ -10375,7 +10559,7 @@
wire [31:0] o = {32{i}};
endmodule
-This is then used in a upper level module:
+This is then used in an upper level module:
module ExampInst (o,i);
output o;
@@ -10438,6 +10622,8 @@
expanded `verilog-mode' simply searches up for the closest template.
Thus you can have multiple templates for the same module, just alternate
between the template for an instantiation and the instantiation itself.
+ (For backward compatibility if no template is found above, it
+ will also look below, but do not use this behavior in new designs.)
The module name must be the same as the name of the module in the
instantiation name, and the code \"AUTO_TEMPLATE\" must be in these exact
@@ -10456,6 +10642,9 @@
debugging is completed though, it will result in lots of extra differences
and merge conflicts.
+ Setting `verilog-auto-template-warn-unused' will report errors
+ if any template lines are unused.
+
For example:
/* InstModule AUTO_TEMPLATE (
@@ -10656,7 +10845,7 @@
(when (and (not (member submod verilog-gate-keywords))
(setq submodi (verilog-modi-lookup submod t)))
(setq submoddecls (verilog-modi-get-decls submodi))
- ;; If there's a number in the instantiation, it may be a argument to the
+ ;; If there's a number in the instantiation, it may be an argument to
the
;; automatic variable instantiation program.
(let* ((tpl-info (verilog-read-auto-template submod))
(tpl-regexp (aref tpl-info 0)))
@@ -10670,7 +10859,8 @@
(verilog-decls-get-vars submoddecls)
skip-pins)))
(vl-dir "interfaced"))
- (when sig-list
+ (when (and sig-list
+ verilog-auto-inst-interfaced-ports)
(when (not did-first) (verilog-auto-inst-first) (setq did-first t))
;; Note these are searched for in verilog-read-sub-decls.
(verilog-insert-indent "// Interfaced\n")
@@ -10740,7 +10930,7 @@
parameter PAR;
endmodule
-This is then used in a upper level module:
+This is then used in an upper level module:
module ExampInst (o,i);
parameter PAR;
@@ -10798,7 +10988,7 @@
;; Note this may raise an error
(when (setq submodi (verilog-modi-lookup submod t))
(setq submoddecls (verilog-modi-get-decls submodi))
- ;; If there's a number in the instantiation, it may be a argument to the
+ ;; If there's a number in the instantiation, it may be an argument to
the
;; automatic variable instantiation program.
(let* ((tpl-info (verilog-read-auto-template submod))
(tpl-regexp (aref tpl-info 0)))
@@ -10867,7 +11057,10 @@
(modsubdecls (verilog-modi-get-sub-decls modi))
(sig-list (verilog-signals-not-in
(verilog-decls-get-outputs moddecls)
- (append (verilog-decls-get-vars moddecls)
+ (append (verilog-signals-with ;; ignore typed signals
+ 'verilog-sig-type
+ (verilog-decls-get-outputs moddecls))
+ (verilog-decls-get-vars moddecls)
(verilog-decls-get-assigns moddecls)
(verilog-decls-get-consts moddecls)
(verilog-decls-get-gparams moddecls)
@@ -10935,6 +11128,12 @@
(verilog-insert-definition modi sig-list "reg" indent-pt nil)
(verilog-insert-indent "// End of automatics\n")))))
+(defun verilog-auto-logic-setup ()
+ "Prepare variables due to AUTOLOGIC."
+ (unless verilog-auto-wire-type
+ (set (make-local-variable 'verilog-auto-wire-type)
+ "logic")))
+
(defun verilog-auto-logic ()
"Expand AUTOLOGIC statements, as part of \\[verilog-auto].
Make wire statements using the SystemVerilog logic keyword.
@@ -10951,15 +11150,13 @@
In the future AUTOLOGIC may declare additional identifiers,
while AUTOWIRE will not."
(save-excursion
- (unless verilog-auto-wire-type
- (set (make-local-variable 'verilog-auto-wire-type)
- "logic"))
+ (verilog-auto-logic-setup)
(verilog-auto-wire)))
(defun verilog-auto-wire ()
"Expand AUTOWIRE statements, as part of \\[verilog-auto].
Make wire statements for instantiations outputs that aren't
-already declared. `verilog-auto-wire-type' may be used to change
+already declared. `verilog-auto-wire-type' may be used to change
the datatype of the declarations.
Limitations:
@@ -11027,7 +11224,7 @@
(defun verilog-auto-output (&optional with-params)
"Expand AUTOOUTPUT statements, as part of \\[verilog-auto].
Make output statements for any output signal from an /*AUTOINST*/ that
-isn't a input to another AUTOINST. This is useful for modules which
+isn't an input to another AUTOINST. This is useful for modules which
only instantiate other modules.
Limitations:
@@ -11037,7 +11234,7 @@
Verilog 2001 style, else uses Verilog 1995 style.
If any concatenation, or bit-subscripts are missing in the AUTOINSTant's
- instantiation, all bets are off. (For example due to a AUTO_TEMPLATE).
+ instantiation, all bets are off. (For example due to an AUTO_TEMPLATE).
Typedefs must match `verilog-typedef-regexp', which is disabled by default.
@@ -11104,7 +11301,7 @@
(defun verilog-auto-output-every ()
"Expand AUTOOUTPUTEVERY statements, as part of \\[verilog-auto].
Make output statements for any signals that aren't primary inputs or
-outputs already. This makes every signal in the design a output. This is
+outputs already. This makes every signal in the design an output. This is
useful to get Synopsys to preserve every signal in the design, since it
won't optimize away the outputs.
@@ -11164,7 +11361,7 @@
Verilog 2001 style, else uses Verilog 1995 style.
If any concatenation, or bit-subscripts are missing in the AUTOINSTant's
- instantiation, all bets are off. (For example due to a AUTO_TEMPLATE).
+ instantiation, all bets are off. (For example due to an AUTO_TEMPLATE).
Typedefs must match `verilog-typedef-regexp', which is disabled by default.
@@ -11243,7 +11440,7 @@
Verilog 2001 style, else uses Verilog 1995 style.
If any concatenation, or bit-subscripts are missing in the AUTOINSTant's
- instantiation, all bets are off. (For example due to a AUTO_TEMPLATE).
+ instantiation, all bets are off. (For example due to an AUTO_TEMPLATE).
Typedefs must match `verilog-typedef-regexp', which is disabled by default.
@@ -11326,9 +11523,14 @@
Module names must be resolvable to filenames. See `verilog-auto-inst'.
Signals are not inserted in the same order as in the original module,
- though they will appear to be in the same order to a AUTOINST
+ though they will appear to be in the same order to an AUTOINST
instantiating either module.
+ Signals declared as \"output reg\" or \"output wire\" etc will
+ lose the wire/reg declaration so that shell modules may
+ generate those outputs differently. However, \"output logic\"
+ is propagated.
+
An example:
module ExampShell (/*AUTOARG*/);
@@ -11408,22 +11610,25 @@
(verilog-decls-get-interfaces submoddecls)
(append (verilog-decls-get-interfaces moddecls)))))
(forward-line 1)
- (setq sig-list-i (verilog-signals-matching-dir-re
- (verilog-signals-matching-regexp sig-list-i regexp)
- "input" direction-re)
- sig-list-o (verilog-signals-matching-dir-re
- (verilog-signals-matching-regexp sig-list-o regexp)
- "output" direction-re)
- sig-list-io (verilog-signals-matching-dir-re
- (verilog-signals-matching-regexp sig-list-io
regexp)
- "inout" direction-re)
+ (setq sig-list-i (verilog-signals-edit-wire-reg
+ (verilog-signals-matching-dir-re
+ (verilog-signals-matching-regexp sig-list-i
regexp)
+ "input" direction-re))
+ sig-list-o (verilog-signals-edit-wire-reg
+ (verilog-signals-matching-dir-re
+ (verilog-signals-matching-regexp sig-list-o
regexp)
+ "output" direction-re))
+ sig-list-io (verilog-signals-edit-wire-reg
+ (verilog-signals-matching-dir-re
+ (verilog-signals-matching-regexp sig-list-io
regexp)
+ "inout" direction-re))
sig-list-if (verilog-signals-matching-dir-re
(verilog-signals-matching-regexp sig-list-if
regexp)
"interface" direction-re))
(when v2k (verilog-repair-open-comma))
(when (or sig-list-i sig-list-o sig-list-io)
(verilog-insert-indent "// Beginning of automatic in/out/inouts
(from specific module)\n")
- ;; Don't sort them so a upper AUTOINST will match the main module
+ ;; Don't sort them so an upper AUTOINST will match the main module
(verilog-insert-definition modi sig-list-o "output" indent-pt v2k
t)
(verilog-insert-definition modi sig-list-io "inout" indent-pt v2k t)
(verilog-insert-definition modi sig-list-i "input" indent-pt v2k t)
@@ -11450,7 +11655,7 @@
Module names must be resolvable to filenames. See `verilog-auto-inst'.
Signals are not inserted in the same order as in the original module,
- though they will appear to be in the same order to a AUTOINST
+ though they will appear to be in the same order to an AUTOINST
instantiating either module.
An example:
@@ -11501,7 +11706,7 @@
Module names must be resolvable to filenames. See `verilog-auto-inst'.
Signals are not inserted in the same order as in the original module,
- though they will appear to be in the same order to a AUTOINST
+ though they will appear to be in the same order to an AUTOINST
instantiating either module.
An example:
@@ -11624,7 +11829,7 @@
Constant signals:
AUTOSENSE cannot always determine if a `define is a constant or a signal
- (it could be in a include file for example). If a `define or other signal
+ (it could be in an include file for example). If a `define or other signal
is put into the AUTOSENSE list and is not desired, use the AUTO_CONSTANT
declaration anywhere in the module (parenthesis are required):
@@ -11726,9 +11931,9 @@
and should not be automatically reset. This includes omitting any signals
used on the right hand side of assignments.
-By default, AUTORESET will include the width of the signal in the autos,
-this is a recent change. To control this behavior, see
-`verilog-auto-reset-widths'.
+By default, AUTORESET will include the width of the signal in the
+autos, SystemVerilog designs may want to change this. To control
+this behavior, see `verilog-auto-reset-widths'.
AUTORESET ties signals to deasserted, which is presumed to be zero.
Signals that match `verilog-active-low-regexp' will be deasserted by tying
@@ -11806,7 +12011,7 @@
(if (assoc (verilog-sig-name sig) dly-list)
(concat " <= " verilog-assignment-delay)
" = ")
- (verilog-sig-tieoff sig (not verilog-auto-reset-widths))
+ (verilog-sig-tieoff sig)
";\n")
(setq sig-list (cdr sig-list))))
(verilog-insert-indent "// End of automatics")))))
@@ -11831,6 +12036,9 @@
`verilog-auto-wire-type' may be used to change the datatype of
the declarations.
+`verilog-auto-reset-widths' may be used to change how the tieoff
+value's width is generated.
+
An example of making a stub for another module:
module ExampStub (/*AUTOINST*/);
@@ -11893,6 +12101,73 @@
(setq sig-list (cdr sig-list))))
(verilog-insert-indent "// End of automatics\n")))))
+(defun verilog-auto-undef ()
+ "Expand AUTOUNDEF statements, as part of \\[verilog-auto].
+Take any `defines since the last AUTOUNDEF in the current file
+and create `undefs for them. This is used to insure that
+file-local defines do not polute the global `define name space.
+
+Limitations:
+ AUTOUNDEF presumes any identifier following `define is the
+ name of a define. Any `ifdefs are ignored.
+
+ AUTOUNDEF suppresses creating an `undef for any define that was
+ `undefed before the AUTOUNDEF. This may be used to work around
+ the ignoring of `ifdefs as shown below.
+
+An example:
+
+ `define XX_FOO
+ `define M_BAR(x)
+ `define M_BAZ
+ ...
+ `ifdef NEVER
+ `undef M_BAZ // Emacs will see this and not `undef M_BAZ
+ `endif
+ ...
+ /*AUTOUNDEF*/
+
+Typing \\[verilog-auto] will make this into:
+
+ ...
+ /*AUTOUNDEF*/
+ // Beginning of automatic undefs
+ `undef XX_FOO
+ `undef M_BAR
+ // End of automatics
+
+You may also provide an optional regular expression, in which case only
+defines the regular expression will be undefed."
+ (save-excursion
+ (let* ((params (verilog-read-auto-params 0 1))
+ (regexp (nth 0 params))
+ (indent-pt (current-indentation))
+ (end-pt (point))
+ defs def)
+ (save-excursion
+ ;; Scan from beginnng of file, or last AUTOUNDEF
+ (or (verilog-re-search-backward-quick "/\\*AUTOUNDEF\\>" end-pt t)
+ (goto-char (point-min)))
+ (while (verilog-re-search-forward-quick
+ "`\\(define\\|undef\\)\\s-*\\([a-zA-Z_][a-zA-Z_0-9]*\\)" end-pt
t)
+ (cond ((equal (match-string-no-properties 1) "define")
+ (setq def (match-string-no-properties 2))
+ (when (and (or (not regexp)
+ (string-match regexp def))
+ (not (member def defs))) ;; delete-dups not in 21.1
+ (setq defs (cons def defs))))
+ (t
+ (setq defs (delete (match-string-no-properties 2) defs))))))
+ ;; Insert
+ (setq defs (sort defs 'string<))
+ (when defs
+ (forward-line 1)
+ (verilog-insert-indent "// Beginning of automatic undefs\n")
+ (while defs
+ (verilog-insert-indent "`undef " (car defs) "\n")
+ (setq defs (cdr defs)))
+ (verilog-insert-indent "// End of automatics\n")))))
+
(defun verilog-auto-unused ()
"Expand AUTOUNUSED statements, as part of \\[verilog-auto].
Replace the /*AUTOUNUSED*/ comment with a comma separated list of all unused
@@ -11981,17 +12256,17 @@
(defun verilog-auto-ascii-enum ()
"Expand AUTOASCIIENUM statements, as part of \\[verilog-auto].
-Create a register to contain the ASCII decode of a enumerated signal type.
+Create a register to contain the ASCII decode of an enumerated signal type.
This will allow trace viewers to show the ASCII name of states.
-First, parameters are built into a enumeration using the synopsys enum
+First, parameters are built into an enumeration using the synopsys enum
comment. The comment must be between the keyword and the symbol.
\(Annoying, but that's what Synopsys's dc_shell FSM reader requires.)
Next, registers which that enum applies to are also tagged with the same
enum.
-Finally, a AUTOASCIIENUM command is used.
+Finally, an AUTOASCIIENUM command is used.
The first parameter is the name of the signal to be decoded.
@@ -12001,17 +12276,19 @@
tell viewers like Dinotrace to display in ASCII format.
The third optional parameter is a string which will be removed
- from the state names. It defaults to "" which removes nothing.
+ from the state names. It defaults to \"\" which removes nothing.
The fourth optional parameter is \"onehot\" to force one-hot
- decoding. If unspecified, if and only if the first parameter
+ decoding. If unspecified, if and only if the first parameter
width is 2^(number of states in enum) and does NOT match the
- width of the enum, the signal is assumed to be a one hot
+ width of the enum, the signal is assumed to be a one-hot
decode. Otherwise, it's a normal encoded state vector.
`verilog-auto-wire-type' may be used to change the datatype of
the declarations.
+ \"auto enum\" may be used in place of \"synopsys enum\".
+
An example:
//== State enumeration
@@ -12066,7 +12343,7 @@
(undecode-sig (or (assoc undecode-name sig-list-all)
(error "%s: Signal %s not found in design"
(verilog-point-text) undecode-name)))
(undecode-enum (or (verilog-sig-enum undecode-sig)
- (error "%s: Signal %s does not have a enum tag"
(verilog-point-text) undecode-name)))
+ (error "%s: Signal %s does not have an enum tag"
(verilog-point-text) undecode-name)))
;;
(enum-sigs (verilog-signals-not-in
(or (verilog-signals-matching-enum sig-list-consts
undecode-enum)
@@ -12159,12 +12436,39 @@
(string-to-number (match-string 2)))))
t t))))
+(defun verilog-auto-template-lint ()
+ "Check AUTO_TEMPLATEs for unused lines.
+Enable with `verilog-auto-template-warn-unused'."
+ (let ((name1 (or (buffer-file-name) (buffer-name))))
+ (save-excursion
+ (goto-char (point-min))
+ (while (re-search-forward
+ "^\\s-*/?\\*?\\s-*[a-zA-Z0-9`_$]+\\s-+AUTO_TEMPLATE" nil t)
+ (let* ((tpl-info (verilog-read-auto-template-middle))
+ (tpl-list (aref tpl-info 1))
+ (tlines (append (nth 0 tpl-list) (nth 1 tpl-list)))
+ tpl-ass)
+ (while tlines
+ (setq tpl-ass (car tlines)
+ tlines (cdr tlines))
+ ;;;
+ (unless (or (not (eval-when-compile (fboundp 'make-hash-table))) ;;
Not supported, no warning
+ (not verilog-auto-template-hits)
+ (gethash (vector (nth 2 tpl-ass) (nth 3 tpl-ass))
+ verilog-auto-template-hits))
+ (verilog-warn-error "%s:%d: AUTO_TEMPLATE line unused: \".%s
(%s)\""
+ name1
+ (+ (elt tpl-ass 3) ;; Template line number
+ (count-lines (point-min) (point)))
+ (elt tpl-ass 0) (elt tpl-ass 1))
+ )))))))
+
;;
;; Auto top level
;;
-(defun verilog-auto (&optional inject) ; Use verilog-inject-auto instead of
passing a arg
+(defun verilog-auto (&optional inject) ; Use verilog-inject-auto instead of
passing an arg
"Expand AUTO statements.
Look for any /*AUTO...*/ commands in the code, as used in
instantiations or argument headers. Update the list of signals
@@ -12219,6 +12523,7 @@
`verilog-auto-reset' for AUTORESET flop resets
`verilog-auto-sense' for AUTOSENSE always sensitivity lists
`verilog-auto-tieoff' for AUTOTIEOFF output tieoffs
+ `verilog-auto-undef' for AUTOUNDEF `undef of local `defines
`verilog-auto-unused' for AUTOUNUSED unused inputs/inouts
`verilog-auto-wire' for AUTOWIRE instantiation wires
@@ -12232,21 +12537,15 @@
(unless noninteractive (message "Updating AUTOs..."))
(if (fboundp 'dinotrace-unannotate-all)
(dinotrace-unannotate-all))
- (let ((oldbuf (if (not (buffer-modified-p))
- (buffer-string)))
- ;; Before version 20, match-string with font-lock returns a
- ;; vector that is not equal to the string. IE if on "input"
- ;; nil==(equal "input" (progn (looking-at "input") (match-string 0)))
- (fontlocked (when (and (boundp 'font-lock-mode)
- font-lock-mode)
- (font-lock-mode 0)
- t))
- ;; Cache directories; we don't write new files, so can't change
- (verilog-dir-cache-preserving t)
- ;; Cache current module
- (verilog-modi-cache-current-enable t)
- (verilog-modi-cache-current-max (point-min)) ; IE it's invalid
- verilog-modi-cache-current)
+ (verilog-save-font-mods
+ (let ((oldbuf (if (not (buffer-modified-p))
+ (buffer-string)))
+ ;; Cache directories; we don't write new files, so can't change
+ (verilog-dir-cache-preserving t)
+ ;; Cache current module
+ (verilog-modi-cache-current-enable t)
+ (verilog-modi-cache-current-max (point-min)) ; IE it's invalid
+ verilog-modi-cache-current)
(unwind-protect
;; Disable change hooks for speed
;; This let can't be part of above let; must restore
@@ -12257,6 +12556,8 @@
;; Wipe cache; otherwise if we AUTOed a block above this one,
;; we'll misremember we have generated IOs, confusing AUTOOUTPUT
(setq verilog-modi-cache-list nil)
+ ;; Local state
+ (setq verilog-auto-template-hits nil)
;; If we're not in verilog-mode, change syntax table so parsing
works right
(unless (eq major-mode `verilog-mode) (verilog-mode))
;; Allow user to customize
@@ -12272,6 +12573,8 @@
(when verilog-auto-read-includes
(verilog-read-includes)
(verilog-read-defines nil nil t))
+ ;; Setup variables due to SystemVerilog expansion
+ (verilog-auto-re-search-do "/\\*AUTOLOGIC\\*/"
'verilog-auto-logic-setup)
;; This particular ordering is important
;; INST: Lower modules correct, no internal dependencies, FIRST
(verilog-preserve-modi-cache
@@ -12284,7 +12587,7 @@
(verilog-inject-arg))
;;
;; Do user inserts first, so their code can insert AUTOs
- ;; We may provide a AUTOINSERTLISPLAST if another cleanup pass
is needed
+ ;; We may provide an AUTOINSERTLISPLAST if another cleanup pass
is needed
(verilog-auto-re-search-do "/\\*AUTOINSERTLISP(.*?)\\*/"
'verilog-auto-insert-lisp)
;; Expand instances before need the signals the instances
input/output
@@ -12313,6 +12616,8 @@
(verilog-auto-re-search-do "/\\*AUTOINOUT\\*/"
'verilog-auto-inout)
;; Then tie off those in/outs
(verilog-auto-re-search-do "/\\*AUTOTIEOFF\\*/"
'verilog-auto-tieoff)
+ ;; These can be anywhere after AUTOINSERTLISP
+ (verilog-auto-re-search-do
"/\\*AUTOUNDEF\\((\"[^\"]*\")\\)?\\*/" 'verilog-auto-undef)
;; Wires/regs must be after inputs/outputs
(verilog-auto-re-search-do "/\\*AUTOLOGIC\\*/"
'verilog-auto-logic)
(verilog-auto-re-search-do "/\\*AUTOWIRE\\*/" 'verilog-auto-wire)
@@ -12326,7 +12631,9 @@
(verilog-auto-re-search-do "/\\*AUTOARG\\*/" 'verilog-auto-arg)
;; Fix line numbers (comments only)
(when verilog-auto-inst-template-numbers
- (verilog-auto-templated-rel))))
+ (verilog-auto-templated-rel))
+ (when verilog-auto-template-warn-unused
+ (verilog-auto-template-lint))))
;;
(verilog-run-hooks 'verilog-auto-hook)
;;
@@ -12343,9 +12650,8 @@
;; End of after-change protection
)))
;; Unwind forms
- (progn
- ;; Restore font-lock
- (when fontlocked (font-lock-mode t))))))
+ ;; Currently handled in verilog-save-font-mods
+ ))))
;;
@@ -12650,7 +12956,7 @@
(define-skeleton verilog-sk-def-reg
"Insert a reg definition."
()
- > "reg [" '(verilog-sk-prompt-width) | -1 verilog-sk-signal ";" \n
(verilog-pretty-declarations) )
+ > "reg [" '(verilog-sk-prompt-width) | -1 verilog-sk-signal ";" \n
(verilog-pretty-declarations-auto) )
(defun verilog-sk-define-signal ()
"Insert a definition of signal under point at top of module."
@@ -12914,9 +13220,12 @@
(concat "verilog-mode v" verilog-mode-version)
'(
verilog-active-low-regexp
+ verilog-after-save-font-hook
verilog-align-ifelse
verilog-assignment-delay
verilog-auto-arg-sort
+ verilog-auto-declare-nettype
+ verilog-auto-delete-trailing-whitespace
verilog-auto-endcomments
verilog-auto-hook
verilog-auto-ignore-concat
@@ -12925,23 +13234,32 @@
verilog-auto-input-ignore-regexp
verilog-auto-inst-column
verilog-auto-inst-dot-name
+ verilog-auto-inst-interfaced-ports
verilog-auto-inst-param-value
+ verilog-auto-inst-sort
verilog-auto-inst-template-numbers
verilog-auto-inst-vector
verilog-auto-lineup
verilog-auto-newline
verilog-auto-output-ignore-regexp
verilog-auto-read-includes
+ verilog-auto-reset-blocking-in-non
verilog-auto-reset-widths
verilog-auto-save-policy
verilog-auto-sense-defines-constant
verilog-auto-sense-include-inputs
verilog-auto-star-expand
verilog-auto-star-save
+ verilog-auto-template-warn-unused
+ verilog-auto-tieoff-declaration
+ verilog-auto-tieoff-ignore-regexp
verilog-auto-unused-ignore-regexp
+ verilog-auto-wire-type
verilog-before-auto-hook
verilog-before-delete-auto-hook
verilog-before-getopt-flags-hook
+ verilog-before-save-font-hook
+ verilog-cache-enabled
verilog-case-indent
verilog-cexp-indent
verilog-compiler
@@ -12949,6 +13267,8 @@
verilog-delete-auto-hook
verilog-getopt-flags-hook
verilog-highlight-grouping-keywords
+ verilog-highlight-includes
+ verilog-highlight-modules
verilog-highlight-p1800-keywords
verilog-highlight-translate-off
verilog-indent-begin-after-if
@@ -12966,11 +13286,15 @@
verilog-linter
verilog-minimum-comment-distance
verilog-mode-hook
+ verilog-mode-release-date
+ verilog-mode-release-emacs
+ verilog-mode-version
verilog-preprocessor
verilog-simulator
verilog-tab-always-indent
verilog-tab-to-comment
verilog-typedef-regexp
+ verilog-warn-fatal
)
nil nil
(concat "Hi Mac,
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