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Re: [ft-devel] FT_New_Memory_Face: get error code 2 on arm


From: duhuanpeng
Subject: Re: [ft-devel] FT_New_Memory_Face: get error code 2 on arm
Date: Thu, 15 Mar 2018 11:11:04 +0800

-----Original Message-----
From: Alexei Podtelezhnikov [mailto:address@hidden 
Sent: Thursday, March 15, 2018 4:00 AM
To: duhuanpeng; freetype-devel
Subject: Re: [ft-devel] FT_New_Memory_Face: get error code 2 on arm

On Wed, Mar 14, 2018 at 9:22 AM, duhuanpeng <address@hidden> wrote:
> My cortex-m0 board is using a armcc(rvct) with keil 5.22a I can send 
> me my whole project if you wish.

Please try "addw" instead of "add" in the assembler code.
addw   a,  a,  #0x8000         /* a  += 0x8000 */
Then we can think how to merge ARMCC and GNUC assembly versions.

0x8000 takes at least 8+(log32/log(n)) bits. n is 5 , 
So 0x8000 is a 13 bit number.
The thumb code is 16 bit machine code.
So, "add a, a, #0x8000" will be translated in to at least two machine code. 



"aplusb.s" 40L, 1054C written                                                   
   
address@hidden:~/asm$ armcc aplusb.s 
"aplusb.s", line 13: Error: A1617E: Specified width is not supported by the 
current instruction set
   13 00000006  add.w r0, r0, #0x8000
"aplusb.s", line 34: Error: A1312E: Assertion failed
   34 00000004         ASSERT {INTER} = {TRUE}
2 Errors, 0 Warnings



Hi, here is my experiment:
C program: aplusb.c 

int plusa(int a)
{
        a += 0x8000;
        return a;
}

; generated by Component: ARM Compiler 5.06 update 3 (build 30
0) Tool: armcc [4d35f0]
; commandline armcc [-S --cpu=Cortex-M0 -O3 aplusb.c]
        THUMB
        REQUIRE8
        PRESERVE8

        AREA ||.text||, CODE, READONLY, ALIGN=1

plusa PROC
        MOVS     r1,#1
        LSLS     r1,r1,#15
        ADDS     r0,r0,r1
        BX       lr
        ENDP


        AREA ||.arm_vfe_header||, DATA, READONLY, NOALLOC, ALIGN=2

; generated by Component: ARM Compiler 5.06 update 3 (build 30
0) Tool: armcc [4d35f0]
; commandline armcc [-S --cpu=Cortex-R4 -O3 aplusb.c]
        ARM
        REQUIRE8
        PRESERVE8

        AREA ||.text||, CODE, READONLY, ALIGN=2

plusa PROC
        ADD      r0,r0,#0x8000
        BX       lr
        ENDP


        AREA ||.arm_vfe_header||, DATA, READONLY, NOALLOC, ALI
GN=2

        DCD      0x00000000


        .cpu cortex-m0
        .eabi_attribute 20, 1
        .eabi_attribute 21, 1
        .eabi_attribute 23, 3
        .eabi_attribute 24, 1
        .eabi_attribute 25, 1
        .eabi_attribute 26, 1
        .eabi_attribute 30, 2
        .eabi_attribute 34, 0
        .eabi_attribute 18, 4
        .file   "aplusb.c"
        .text
        .align  1
        .p2align 2,,3
        .global plusa
        .syntax unified
        .code   16
        .thumb_func
        .fpu softvfp
        .type   plusa, %function
plusa:
        @ args = 0, pretend = 0, frame = 0
        @ frame_needed = 0, uses_anonymous_args = 0
        @ link register save eliminated.
        movs    r3, #128
        lsls    r3, r3, #8
        mov     ip, r3
        @ sp needed
        add     r0, r0, ip
        bx      lr
        .size   plusa, .-plusa
        .ident  "GCC: (GNU Tools for Arm Embedded Processors 7-2017-q4-major) 
7.2.1 20170904 (release
) [ARM/embedded-7-branch revision 255204]"





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