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Re: [Gnucap-devel] Verilog - was: Re: Use of M as suffix for Mega
From: |
al davis |
Subject: |
Re: [Gnucap-devel] Verilog - was: Re: Use of M as suffix for Mega |
Date: |
Tue, 5 Sep 2006 14:55:30 -0400 |
User-agent: |
KMail/1.9.4 |
On Thursday 24 August 2006 20:11, jbdavid wrote:
> 1. I'd strongly suggest perl or python as scripting languages
> for netlist translation..
> a friend of mine had once done a spice-spectre-Verilog-AMS
> netlist translator that
> used an internal XML table and XSLT transformations..
> everything in to XML database, then out to whichever format
> you wanted.. I can ask him if he'd be willing to contribute
> that.
I will take it no matter what language it is written in.
The reason I suggested awk is that for simple translations it is
just a list of expressions to match and print statements to
print them different. For simple translations it is by far the
simplest. For complex translations, I would prefer a language
more tuned to complex problems, like python.
There is a big difference in the style of these languages. I
find the idea of perl being a "super awk" a bit strange. awk
is a "logic" language. perl is an "imperitive" language. The
programming style is completely different. I think many of
those who automatically recommend against awk are not
comfortable with the logic style programming.
The classic logic language is prolog. awk and make are also
logic languages.
> 2. What is different about the cadence AMSDesigner is that
> the digital and analog are VERY closely integrated.. you can
> use both digital and analog constructs in the same module..
> Pretty sweet.. I'd like the same capability in a free tool,
> so I'm willing to help work on it..
I would like to know more about the user experience. What is
the command set like? etc...
> In fact after working with spectre (which at least had case
> sensitivity) I really want a simulator with Verilog syntax as
> the primary netlisting language..
So do I.
> IE a Joint icarus/gnucap build..
That is something to look into ,, A big difference is that
icarus is compiled, gnucap is interpreted. Gnucap has the
provision for attaching compiled models, which will become more
automatic than it is. By doing this, ultimately almost
anything could be attached.
Also, I would like to look into adding analog to icarus..
> (but the XML idea keeps sticking in the back of my head
The XML idea keeps coming up, but really doesn't help much here.
In this context, XML is just a syntax. Everything else still
needs to be defined. Instead of XML, one might as well say to
use a C-like syntax, an ADA like syntax, or a python like
syntax. The syntax is the easy part. The meaning is the hard
part. That's why Verilog and VHDL are so attractive.
> too..) just tell me where the subversion code repository is
> and how to check out the code..
The best way for now is the development snapshots. The RCS
archive is at http://www.gnucap.org/RCS . I haven't figured
out how to get clean web access. I plan to migrate it over to
CVS or something newer, but have been swamped with other stuff.
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