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[Guile-commits] 01/01: Recognize RISC-V compilation targets.
From: |
Mark H. Weaver |
Subject: |
[Guile-commits] 01/01: Recognize RISC-V compilation targets. |
Date: |
Thu, 15 Mar 2018 23:18:14 -0400 (EDT) |
mhw pushed a commit to branch stable-2.0
in repository guile.
commit d6e669b8cb26f870ea6611a54788b75fbad67bbe
Author: Shea Levy <address@hidden>
Date: Sun Feb 25 20:34:39 2018 -0500
Recognize RISC-V compilation targets.
* module/system/base/target.scm (cpu-endianness): Add case for "riscv"
variants.
Signed-off-by: Shea Levy <address@hidden>
Signed-off-by: Mark H Weaver <address@hidden>
---
module/system/base/target.scm | 2 ++
1 file changed, 2 insertions(+)
diff --git a/module/system/base/target.scm b/module/system/base/target.scm
index fbead44..105c581 100644
--- a/module/system/base/target.scm
+++ b/module/system/base/target.scm
@@ -80,6 +80,8 @@
(endianness big))
((string=? "aarch64" cpu)
(endianness little))
+ ((string-match "riscv[1-9][0-9]*" cpu)
+ (endianness little))
(else
(error "unknown CPU endianness" cpu)))))