[guss-commit] guss ChangeLog Makefile.am Makefile.in TODO con...

[Johan Rydberg]

CVSROOT:        /cvsroot/guss
Module name:    guss
Changes by:     Johan Rydberg <address@hidden>  02/06/19 14:53:22

Modified files:
        .              : ChangeLog Makefile.am Makefile.in TODO 
                         configure configure.in host-i386.h hw-core.c 
                         hw-cpu.c hw.c sim-cpu.c sim-cpu.h sim-endian.h 
                         sim-engine.c sim-scache.c toplevel.c 

Log message:
        * configure.in: Add OpenRISC target.
        * configure: Regenerate.
        
        * Makefile.am: Add OpenRISC dependencies.
        * Makefile.in: Regenerate.
        
        * TODO: Removed some notes, added a few.
        
        * sim-cpu.c (sim_cpu_prepare_run): Just set sim_cpu
        to CPU.  Everything else is moed to sim_engine_run_full.
        
        * sim-engine.c (sim_engine_run_full): Set virtual PC
        here, instead of in sim_cpu_prepare_run.
        (sim_engine_requalify): Implemented.
        
        * hw-core.c (core_memory_read): Add data to execute
        STC aswell.  Correct mask.
        (core_memory_write): Correct mask.
        (core_io_write): Check so that we got any I/O mappings.
        (core_io_read): Likewise.
        
        * hw.c: Add hw_tick_description.
        
        * sim-endian.h (_SWAP4) [i386]: Just test for i386.
        
        * hw-cpu.c (hw_cpu_trigger_interrupt): Handle interrupts
        by calling HANDLE_EXTERNAL_INTERRUPT.
        
        * sim-cpu.h (sim_xpc): Declare.
        
        * toplevel.c (run_command): Print reason for simulation
        to stop.
        
        * host-i386.h (SEM_INSN_EPILOGUE) [HAVE_DELAY_SLOT]:
        Special definition.
        
        * sim-scache.c (sim_scache_get_page): Break out of loop at
        the last cache entry, not after it.

CVSWeb URLs:
http://savannah.gnu.org/cgi-bin/viewcvs/guss/guss/ChangeLog.diff?tr1=1.8&tr2=1.9&r1=text&r2=text
http://savannah.gnu.org/cgi-bin/viewcvs/guss/guss/Makefile.am.diff?tr1=1.5&tr2=1.6&r1=text&r2=text
http://savannah.gnu.org/cgi-bin/viewcvs/guss/guss/Makefile.in.diff?tr1=1.5&tr2=1.6&r1=text&r2=text
http://savannah.gnu.org/cgi-bin/viewcvs/guss/guss/TODO.diff?tr1=1.2&tr2=1.3&r1=text&r2=text
http://savannah.gnu.org/cgi-bin/viewcvs/guss/guss/configure.diff?tr1=1.2&tr2=1.3&r1=text&r2=text
http://savannah.gnu.org/cgi-bin/viewcvs/guss/guss/configure.in.diff?tr1=1.2&tr2=1.3&r1=text&r2=text
http://savannah.gnu.org/cgi-bin/viewcvs/guss/guss/host-i386.h.diff?tr1=1.2&tr2=1.3&r1=text&r2=text
http://savannah.gnu.org/cgi-bin/viewcvs/guss/guss/hw-core.c.diff?tr1=1.4&tr2=1.5&r1=text&r2=text
http://savannah.gnu.org/cgi-bin/viewcvs/guss/guss/hw-cpu.c.diff?tr1=1.1.1.1&tr2=1.2&r1=text&r2=text
http://savannah.gnu.org/cgi-bin/viewcvs/guss/guss/hw.c.diff?tr1=1.2&tr2=1.3&r1=text&r2=text
http://savannah.gnu.org/cgi-bin/viewcvs/guss/guss/sim-cpu.c.diff?tr1=1.1.1.1&tr2=1.2&r1=text&r2=text
http://savannah.gnu.org/cgi-bin/viewcvs/guss/guss/sim-cpu.h.diff?tr1=1.2&tr2=1.3&r1=text&r2=text
http://savannah.gnu.org/cgi-bin/viewcvs/guss/guss/sim-endian.h.diff?tr1=1.2&tr2=1.3&r1=text&r2=text
http://savannah.gnu.org/cgi-bin/viewcvs/guss/guss/sim-engine.c.diff?tr1=1.4&tr2=1.5&r1=text&r2=text
http://savannah.gnu.org/cgi-bin/viewcvs/guss/guss/sim-scache.c.diff?tr1=1.2&tr2=1.3&r1=text&r2=text
http://savannah.gnu.org/cgi-bin/viewcvs/guss/guss/toplevel.c.diff?tr1=1.5&tr2=1.6&r1=text&r2=text