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Re: confused by emacs verilog mode
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From: |
Stefan Monnier |
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Subject: |
Re: confused by emacs verilog mode |
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Date: |
Sun, 25 May 2014 15:36:00 -0400 |
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User-agent: |
Gnus/5.13 (Gnus v5.13) Emacs/24.4.50 (gnu/linux) |
>> I'm trying to use emacs verilog mode for vi. I have a piece of code
>> like this:
[...]
>> what confused me is that after generate code, it seems like this:
[...]
>> you can find from these code that the dataout0_r_entry_xxx has been
>> changed from dataout0 to dataout1. I don't know how this happens and
>> how can i get right code. Can anybody help me? thanks.
You say "after generate code", but I have no idea what that step
refers to. What makes you think this has to do with Emacs?
Stefan