(no subject)

[Jose Maria Rodriguez Millan]

Hello,
Please,can you help me with this doubt about makefile?

     I've the following scenario:
     Have a group of targets (libs), each one in a separate directory,say
     a/liba.a
     b/libb.a
     c/libc.a
     The commands to make all them are the same;not so the
prerrequisites,but they can be computed from the
      target names,but just in case $(@D) is already defined by makefile
when expanding the prerrequisites.

    For example,if each lib directory has a src subdirectory
(a/src,b/src,c/src) ,i can get the list of prerrequisites
    with
                    $(subst .cc,.o,$(wildcard $(addsuffix /src/*.cc,$(@D))))

    but this expression seems not to work if written as prerrequisite (i
suppose because $(@D) is defined only when
    command execution begins.If it were so ,would not be interesting to have
target-related variables already defined
    when computing prerrequisites?))

    In the end,what i want to do is:
    PROJECTLIBS=a/liba.a\
    b/libb.a\
    c/libc.a

    $(PROJECTLIBS) : <calculate prerrequisites,based in current target path>
                    <commands>

    Is this possible?Is there any other way to do the same thing?

Thanks for your help and time,

Jose