Re: Make must be executed twice

[Boris Kolpackov]

lists <address@hidden> writes:

> -
> include /obvious_definitions.mk
>
> DIRS := $(BUILD_DIR)
> BUILD_DIR := /build
> CLUSTER_NAME := importers
> EXEC_SRCS := import_e.cc
> SRCS_LIST := /importers/import_e.cc
>
> EXECS := $(EXEC_SRCS:.cc=)
> DEP  := $(SRCS:.cc=.d)
>
> bin: links import_e
>
> import_e: import_e.o
>     $(CXX) -o $@ $(FLAGS) $<
>
> links: $(DIRS)
>     @ln -sf $(SRCS_LIST) $(BUILD_DIR)
>
> $(DIRS):
>     @echo Creating install dir $@
>     @$(INSTALL) -d $@
>
> %.o: %.cc
>     $(CXX) $(MAKEDEPFLAGS) -c $(FLAGS) $<
>
> .PHONY: clean bin links
>
> # Include dependencies
> ifdef DEP
> ifneq ($(MAKECMDGOALS),clean)
> -include $(DEP)
> endif
> endif # DEP
> -
>
> When I execute the make command, either with an empty build directory or
> no build directory, I get an error that there's no target for
> import_e.o.  If I run make twice, it's happy.

It's because you are hiding stuff from make. For example, make has no
way of guessing that 'links' target will create a .cc file in the /build
directory. Try to do everything explicitly:


bin: $(BUILD_DIR)/import_e

#
#
$(BUILD_DIR)/import_e: $(BUILD_DIR)/import_e.o | $(BUILD_DIR)/.
    $(CXX) -o $@ $(FLAGS) $<

#
#
.PRECIOUS: $(BUILD_DIR)/%.cc

$(BUILD_DIR)/%.cc: $(SRCS_DIR)/%.cc | $(BUILD_DIR)/.
    @ln -s $< $@

#
#
$(BUILD_DIR)/%.o: $(BUILD_DIR)/%.cc | $(BUILD_DIR)/.
    $(CXX) $(MAKEDEPFLAGS) -c $(FLAGS) $<


#
#
.PRECIOUS: %/.

%/.:
    mkdir -p $@


-boris