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Problem with makefile
From: |
Hiebert, Darren (IS) |
Subject: |
Problem with makefile |
Date: |
Wed, 6 Mar 2013 18:30:39 +0000 |
For a reason I have been unable to determine, the attached makefile does not
behave the same way for three ways of expanding a variable. These three methods
are at lines 11-13 of the attached makefile.
In particular, the target_assignments function assigns some new variables based
upon a parameterized name (in this case SAMPLE) and predefined variables based
upon the name.
Executing the command "make print-SAMPLE_BIN1_OBJECT_FILES" (triggered by the
expansion at line 11) displays the properly-set variable
SAMPLE_BIN1_OBJECT_FILES = sampledir/sample1.o, as does executing the command
"make print-SAMPLE_BIN2_OBJECT_FILES" (triggered by the expansion at line 12)
displays the properly-set variable SAMPLE_BIN2_OBJECT_FILES =
sampledir/sample2.o. However, executing the command "make
print-SAMPLE_BIN3_OBJECT_FILES" (triggered by the expansion at line 13) DOES
NOT show any value assigned to variable SAMPLE_BIN3_OBJECT_FILES.
Executing the target "make template" shows the expanded template and shows that
the three expansions triggered by lines 17-19 all mirror each other, which
leaves my clueless as to why the last one fails.
Is there anyone who can explain to me why the expansion triggered by line 13
does not properly assign a value to SAMPLE_BIN3_OBJECT_FILES?
Thank you in advance,
Darren
If for some reason the attachment is trimmed from this email, here is the text
of the Makefile:
--------------------------------------------
define target_assignments
ifneq "$$(strip $$($(1)_$(2)_TARGET))" ""
$(1)_$(2)_OBJECT_FILES := $$(addprefix $$($(2)_DIR),$$($(1)_$(2)_OBJECTS))
endif
endef
define template
$(1)_TARGET_DIR ?= $($(1)_DIR)
$(1)_TARGET_NUMBERS ?= 3
$(call target_assignments,$(1),BIN1)
$(foreach index,2,$(call target_assignments,$(1),BIN$(index)))
$(foreach index,$($(1)_TARGET_NUMBERS),$(call
target_assignments,$(1),BIN$(index)))
.PHONY: expansion
expansion:
@ cat Makefile > .tmp.mak
@ echo '$$$$(info $$$$(call template,$(1)))' >> .tmp.mak
@ echo 'nada:' >> .tmp.mak
@ $$(MAKE) -f .tmp.mak nada
@ rm -f .tmp.mak
endef
SAMPLE_DIR = sampledir/
SAMPLE_BIN1_TARGET = sample1
SAMPLE_BIN1_OBJECTS = sample1.o
SAMPLE_BIN2_TARGET = sample2
SAMPLE_BIN2_OBJECTS = sample2.o
SAMPLE_BIN3_TARGET = sample3
SAMPLE_BIN3_OBJECTS = sample3.o
$(eval $(call template,SAMPLE))
.PHONY: print-%
print-%:
@echo $* = $($*)
@echo $* origin is $(origin $*)
--------------------------------------------
Makefile
Description: Makefile
- Problem with makefile,
Hiebert, Darren (IS) <=