Re: Avoid to recompile the target

[Kenneth Adam Miller]

If you specify a target that isn't considered satisfied by make after it
executes the command, the next time it runs it will not see the new files,
look for something that will never exist and then rebuild it every time.
Think about this:

all: foo

foo: source.c

gcc source.c


The problem here is you forgot to put -o foo, and therefore, gcc will
generate the default a.out; make will look every time for a file "foo", not
find it, and then try and remake it.

On Mon, Dec 8, 2014 at 9:23 AM, FanKe Meng <address@hidden>
wrote:

> Hi,
>
>
> I'm writing a simple project now with the main Makefile and definitions in
> a directory and submakes in its sub-directories.
>
>
> I write explicit rules to compile the source files into object files and
> the link all the object files into an executable file.
>
>
> However, while there is no source file changed and make is triggered on
> the command line,the executable file will be updated each time
>
>
> though the object files aren't compiled again. Is there a way to avoid it?
>
>
> Any help are appreciated.
>
>
> The Makefile and Makefile.def are here:
>
>
> Makefile
>
>
> all:
>
>
> export all_apps :=
>
>
> include Makefile.def
> include sub1/Makefile
> include sub2/Makefile
>
>
> all : $(all_apps)
>
>
>
>
> Makefile.def
>
>
> def src_to_obj
> $1 : $2
> $(CC) -o $1 -c $2
> endef
>
>
> def make_app
> $(eval objs := $(patsubst %.c, %.o, $1))
> all_apps += $1
> $1 : $(objs)
> $(CC) -o $1 $(objs)       #### it will be run every time make is triggered
> on the command line. Any way to avoid it?
> endef
>
>
> Best regars
> Richy Mong
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>