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Re: Help required in gnumake
From: |
beginner beginner |
Subject: |
Re: Help required in gnumake |
Date: |
Wed, 6 Aug 2003 21:56:54 -0700 (PDT) |
Hi Greg,
I got the point that as mentioned by Paul that If i write
>> ifneq ($(DEF_OBJDIR),$(OBJDIR_UNOPT))
>> ifneq ($(MCC_FLAGS),)
>> @echo test
>> DEF_CC_FLAGS=$(MCC_FLAGS)
>> @echo Test1
would not work because DEF_CC_FLAGS without tab would start new make session
and it will give me error that command commence before first target.
But as mentioned by you wtiting the same as
ifneq ($(DEF_OBJDIR),$(OBJDIR_UNOPT))
>> ifneq ($(MCC_FLAGS),)
>> @echo test
>> DEF_CC_FLAGS=$(MCC_FLAGS)
>> @echo Test1
i.e. putting tab in front of DEF_CC_FLAGS then we will not get any error
but I am getting a strange error.
Start building
Set the value
DEF_OBJDIR=..\obj
process_begin: CreateProcess((null), DEF_OBJDIR=..\obj, ...) failed.
make (e=2): The system cannot find the file specified.
gmake: *** [dhcpclnt.obj] Error 2
Please help.
Thanks,
Amit.
--- Greg Chicares <address@hidden> wrote:
>beginner beginner wrote:
>>
>> %.obj: %.c
>> @echo Start building <<<It works>>>>
>
>The commands in rules are shell commands, and your shell may
>interpret '<' and '>' as redirection, so try '#' instead.
>
>> ifeq ($(DEF_OBJDIR),)
>> @echo Set the value <<<<<<<This echo works fine>>>>>>>
>> DEF_OBJDIR=$(OBJDIR)
>
>The last line didn't begin with a tab, and it's not a blank
>line or a comment, so it can't be a command. This rule's
>list of commands has ended.
>
>> endif
>> #######################################################################################################
>> # Set the DEF_OBJDIR as ..\obj <<<<Can you let me know how to check this
>> value>>>>
>> ########################################################################################################
>> ifneq ($(DEF_OBJDIR),$(OBJDIR_UNOPT))
>> ifneq ($(MCC_FLAGS),)
>> @echo test
>> DEF_CC_FLAGS=$(MCC_FLAGS)
>> else <<<<My Test comes here>>>>>
>
>Here I get 'Extraneous text after `else' directive'.
>Write '#' at the beginning of the comment.
>
>> @echo test <<<<It should print this but give me warning that
>> *** commands commence before first target. Stop.>>>>>>>>
>
>I don't get that diagnostic with this test case; but see below.
>
>> DEF_CC_FLAGS=$(CC_FLAGS)
>> endif
>
>Here I get '*** missing `endif'. Stop.'. So add another 'endif'.
>
>Making the changes suggested above, I then get
>'make: *** No targets. Stop.'
>
>Consider this modified testcase that gets past the syntax errors:
>
>#testcase begins
>all: eraseme.obj
>
>CC_FLAGS =abc
>MCC_FLAGS =def
>
>OBJDIR_UNOPT=ghi
>OBJDIR =jkl
>
>%.obj: %.c
> @echo Start building
>ifeq ($(DEF_OBJDIR),)
> @echo Set the value
> DEF_OBJDIR=$(OBJDIR)
>endif
>ifneq ($(DEF_OBJDIR),$(OBJDIR_UNOPT))
>ifneq ($(MCC_FLAGS),)
> @echo test
> DEF_CC_FLAGS=$(MCC_FLAGS)
>else
> @echo test
> DEF_CC_FLAGS=$(CC_FLAGS)
>endif
>endif
> @echo DEF_OBJDIR is $(DEF_OBJDIR)
> @echo DEF_CC_FLAGS is $(DEF_CC_FLAGS)
>#testcase ends
>
>Note that all commands begin with a tab. Conditional
>directives don't--they're resolved when make reads the
>makefile. But the output is
>
>Start building
>Set the value
>DEF_OBJDIR=jkl
>test
>DEF_CC_FLAGS=def
>DEF_OBJDIR is
>DEF_CC_FLAGS is
>
>This line
> DEF_CC_FLAGS=def
>is a shell command that sets an environment variable.
>But make reads environment variables when it starts
>up, so this shell command doesn't affect the variable's
>value in this rule, which is empty by default:
> DEF_CC_FLAGS is
>
>Probably you're inserting 'echo' lines for debugging
>and don't really want to see the values every time you
>compile a file. Try this:
>
>#testcase begins
>
>CC_FLAGS =abc
>MCC_FLAGS =def
>
>OBJDIR_UNOPT=ghi
>OBJDIR =jkl
>
>ifeq ($(DEF_OBJDIR),)
> DEF_OBJDIR=$(OBJDIR)
>endif
>
>ifneq ($(DEF_OBJDIR),$(OBJDIR_UNOPT))
> ifneq ($(MCC_FLAGS),)
> DEF_CC_FLAGS=$(MCC_FLAGS)
> else
> DEF_CC_FLAGS=$(CC_FLAGS)
> endif
>endif
>
>.PHONY: print_values
>print_values:
> @echo DEF_OBJDIR is $(DEF_OBJDIR)
> @echo DEF_CC_FLAGS is $(DEF_CC_FLAGS)
>#testcase ends
>
>Make the 'print_values' target to see the values:
>
>DEF_OBJDIR is jkl
>DEF_CC_FLAGS is def
>
>By the way, names like $(OBJDIR) suggest that you may
>be creating object files in a directory specified by
>a make variable. See
> http://make.paulandlesley.org/rules.html#rule3
> http://make.paulandlesley.org/multi-arch.html#explicitpath
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