Re: [Openvortex-dev] [PATCH] more eq cleanups / WT engine

[Manuel Jander]

Hi Jeff,

Regarding your patch, it seems ok to me, but i'm unable to test it now.

i have been looking at some documents. This one in particular seems
interesting to me:
http://ddeimos.homelinux.net/~mjander/pat6167465-10.tiff

Extract of patent number 6167465:

After DMA controller 310 has been initialized, CPU 210 initializes FIFO
controller 320 in block 557. DMA flag 505(a) is typically reset since no
DMA request has been sent. The priority of the DMA channel is set in
priority value register 505(b). Empty flag 505(d) may be reset or set
since the corresponding FIFO 306(0) is technically empty, but the empty
flag will be ignored due to the disabling of either interrupt enable
flag 384(c)(0) or 382(f). Data bus pointer 505(e) and DMA pointer 505(f)
are set to the same value, the first entry in FIFO 306(0), since there
is currently no data. Wait for DMA flag 505(h) is set to avoid erroneous
interrupts at start up Wait for DMA flag 505(h) may be reset once
operations have begun. Stereo flag 505(i) may be set or reset
appropriately, depending on the type of DMA channel. Run time modify
flag 505(f) is typically reset in the initialization phase. During later
operations, CPU 210 may set run time modify flag 505(j) when CPU 210 is
performing such an operation. 

Additionally, in block 557, CPU 210 initializes trigger register 506 for
a particular control memory 505. In the exemplary embodiment, enable
default data bus trigger flag 506(b) is reset, and data bus trigger
level 506(d) is set to 16. This operation indicates to FIFO controller
320 that when FIFO 306(0) is half empty a DMA request should be sent. 

Another step in the initialization process is the setting of channel
valid flag 505(c). The channel valid flag indicates that the particular
DMA channel has been activated and the appropriate sub-buffer table
380(0), FIFO control register 505(0) and FIFO 306(0) are active. 

After FIFO controller 320 has been initialized, CPU 210 proceeds to
initialize one of the operational components 341-352 in block 560. One
of the components 341-352 is initialized to be prepared to receive data
from FIFO 306(0) and perform the appropriate operations on the data.
Additionally, data bus 330 is configured to allow for data to be passed
from FIFO 306(0) to the selected component 341-352. If the DMA channel
is a wavetable DMA channel, data may be directly routed from one of
FIFOs 306 to wavetable 342, or via data bus 330. For purposes of
illustration, CPU 210 may select mixer 344 to receive data from FIFO
306(0).

The question is: Is the audio path between the WT fifos toward the
"Wavetable" block/banks hardwired, or is there any need to explicitly
set those routes ? If yes, i really wonder, where the Hell this is done
in the WDM driver.

I trying to figure out why the WT engine does not work. If anyone could
do a review of the WT DMA and au88x0_synth.c code would be great. I
reviewed it many times, but since i did review uncountable times the
FIFO initialization bug too(chip & dale), and did not find it (claudia
found it), maybe somebody else has more luck :P

Best Regards

Manuel Jander

On Wed, 2004-09-08 at 15:28, Jeff Muizelaar wrote:
> some more cleanups of the eq code. 
> 
> Basically make a function called sign_invert that makes positive numbers
> negative and negative numbers positive. This function is then used
> instead of the old '0x8000 -> 0x7fff' code and bitwise not.
> 
> -Jeff
> 
> 
> diff -ur virgin/sound/pci/au88x0/au88x0_eq.c 
> working/sound/pci/au88x0/au88x0_eq.c
> --- virgin/sound/pci/au88x0/au88x0_eq.c       2004-09-08 14:18:17.000000000 
> -0400
> +++ working/sound/pci/au88x0/au88x0_eq.c      2004-09-08 14:33:38.000000000 
> -0400
> @@ -52,37 +52,33 @@
>       hwwrite(vortex->mmio, 0x2b3c8, level);
>  }
>  
> +static inline short sign_invert(short a)
> +{
> +     /* -(-32768) -> -32768 so we do -(-32768) -> 32767 to make the result 
> positive */
> +     if (a == -32768)
> +             return 32767;
> +     else
> +             return -a;
> +}
> +
>  static void vortex_EqHw_SetLeftCoefs(vortex_t * vortex, u16 coefs[])
>  {
>       eqhw_t *eqhw = &(vortex->eq.this04);
> -     int eax, i = 0, n /*esp2c */;
> +     int i = 0, n /*esp2c */;
>  
>       for (n = 0; n < eqhw->this04; n++) {
>               hwwrite(vortex->mmio, 0x2b000 + n * 0x30, coefs[i + 0]);
>               hwwrite(vortex->mmio, 0x2b004 + n * 0x30, coefs[i + 1]);
>  
>               if (eqhw->this08 == 0) {
> -                     hwwrite(vortex->mmio, 0x2b008 + n * 0x30, coefs[i + 2]);
> -                     hwwrite(vortex->mmio, 0x2b00c + n * 0x30, coefs[i + 3]);
> -                     eax = coefs[i + 4];     //esp24;
> +                     hwwrite(vortex->mmio, 0x2b008 + n * 0x30, coefs[i + 2] 
> & 0xffff);
> +                     hwwrite(vortex->mmio, 0x2b00c + n * 0x30, coefs[i + 3] 
> & 0xffff);
> +                     hwwrite(vortex->mmio, 0x2b010 + n * 0x30, coefs[i + 4] 
> & 0xffff);
>               } else {
> -                     if (coefs[2 + i] == 0x8000)
> -                             eax = 0x7fff;
> -                     else
> -                             eax = ~coefs[2 + i];
> -                     hwwrite(vortex->mmio, 0x2b008 + n * 0x30, eax & 0xffff);
> -                     if (coefs[3 + i] == 0x8000)
> -                             eax = 0x7fff;
> -                     else
> -                             eax = ~coefs[3 + i];
> -                     hwwrite(vortex->mmio, 0x2b00c + n * 0x30, eax & 0xffff);
> -                     if (coefs[4 + i] == 0x8000)
> -                             eax = 0x7fff;
> -                     else
> -                             eax = ~coefs[4 + i];
> +                     hwwrite(vortex->mmio, 0x2b008 + n * 0x30, 
> sign_invert(coefs[2 + i]) & 0xffff);
> +                     hwwrite(vortex->mmio, 0x2b00c + n * 0x30, 
> sign_invert(coefs[3 + i]) & 0xffff);
> +                     hwwrite(vortex->mmio, 0x2b010 + n * 0x30, 
> sign_invert(coefs[4 + i]) & 0xffff);
>               }
> -             hwwrite(vortex->mmio, 0x2b010 + n * 0x30, eax);
> -
>               i += 5;
>       }
>  }
> @@ -90,33 +86,21 @@
>  static void vortex_EqHw_SetRightCoefs(vortex_t * vortex, u16 coefs[])
>  {
>       eqhw_t *eqhw = &(vortex->eq.this04);
> -     int i = 0, n /*esp2c */, eax;
> +     int i = 0, n /*esp2c */;
>  
>       for (n = 0; n < eqhw->this04; n++) {
>               hwwrite(vortex->mmio, 0x2b1e0 + n * 0x30, coefs[0 + i]);
>               hwwrite(vortex->mmio, 0x2b1e4 + n * 0x30, coefs[1 + i]);
>  
>               if (eqhw->this08 == 0) {
> -                     hwwrite(vortex->mmio, 0x2b1e8 + n * 0x30, coefs[2 + i]);
> -                     hwwrite(vortex->mmio, 0x2b1ec + n * 0x30, coefs[3 + i]);
> -                     eax = coefs[4 + i];     //*esp24;
> +                     hwwrite(vortex->mmio, 0x2b1e8 + n * 0x30, coefs[2 + i] 
> & 0xffff);
> +                     hwwrite(vortex->mmio, 0x2b1ec + n * 0x30, coefs[3 + i] 
> & 0xffff);
> +                     hwwrite(vortex->mmio, 0x2b1f0 + n * 0x30, coefs[4 + i] 
> & 0xffff);
>               } else {
> -                     if (coefs[2 + i] == 0x8000)
> -                             eax = 0x7fff;
> -                     else
> -                             eax = ~(coefs[2 + i]);
> -                     hwwrite(vortex->mmio, 0x2b1e8 + n * 0x30, eax & 0xffff);
> -                     if (coefs[3 + i] == 0x8000)
> -                             eax = 0x7fff;
> -                     else
> -                             eax = ~coefs[3 + i];
> -                     hwwrite(vortex->mmio, 0x2b1ec + n * 0x30, eax & 0xffff);
> -                     if (coefs[4 + i] == 0x8000)
> -                             eax = 0x7fff;
> -                     else
> -                             eax = ~coefs[4 + i];
> +                     hwwrite(vortex->mmio, 0x2b1e8 + n * 0x30, 
> sign_invert(coefs[2 + i]) & 0xffff);
> +                     hwwrite(vortex->mmio, 0x2b1ec + n * 0x30, 
> sign_invert(coefs[3 + i]) & 0xffff);
> +                     hwwrite(vortex->mmio, 0x2b1f0 + n * 0x30, 
> sign_invert(coefs[4 + i]) & 0xffff);
>               }
> -             hwwrite(vortex->mmio, 0x2b1f0 + n * 0x30, eax);
>               i += 5;
>       }
>  
> @@ -188,22 +172,12 @@
>  static void vortex_EqHw_SetBypassGain(vortex_t * vortex, u16 a, u16 b)
>  {
>       eqhw_t *eqhw = &(vortex->eq.this04);
> -     int eax;
> -
>       if (eqhw->this08 == 0) {
>               hwwrite(vortex->mmio, 0x2b3d4, a);
>               hwwrite(vortex->mmio, 0x2b3ec, b);
>       } else {
> -             if (a == 0x8000)
> -                     eax = 0x7fff;
> -             else
> -                     eax = ~a;
> -             hwwrite(vortex->mmio, 0x2b3d4, eax & 0xffff);
> -             if (b == 0x8000)
> -                     eax = 0x7fff;
> -             else
> -                     eax = ~b;
> -             hwwrite(vortex->mmio, 0x2b3ec, eax & 0xffff);
> +             hwwrite(vortex->mmio, 0x2b3d4, sign_invert(a) & 0xffff);
> +             hwwrite(vortex->mmio, 0x2b3ec, sign_invert(b) & 0xffff);
>       }
>  }
>  
> 
> 
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