[Qemu-arm] [PATCH Trivial] hw/intc/arm_gic: Use pre-defined macro for cpu_num in code

[Wei Huang]

Given that there is a macro, NUM_CPU(s), defined for CPU number in
arm_gic.c, it is better to use it instead of using s->num_cpu in
this file. Code is more consistent after this change.

Signed-off-by: Wei Huang <address@hidden>
---
 hw/intc/arm_gic.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
index 8bad132..4e7733c 100644
--- a/hw/intc/arm_gic.c
+++ b/hw/intc/arm_gic.c
@@ -39,7 +39,7 @@ static const uint8_t gic_id[] = {
 
 static inline int gic_get_current_cpu(GICState *s)
 {
-    if (s->num_cpu > 1) {
+    if (NUM_CPU(s) > 1) {
         return current_cpu->cpu_index;
     }
     return 0;
@@ -643,7 +643,7 @@ static uint32_t gic_dist_readb(void *opaque, hwaddr offset, 
MemTxAttrs attrs)
         res = gic_get_priority(s, cpu, irq, attrs);
     } else if (offset < 0xc00) {
         /* Interrupt CPU Target.  */
-        if (s->num_cpu == 1 && s->revision != REV_11MPCORE) {
+        if (NUM_CPU(s) == 1 && s->revision != REV_11MPCORE) {
             /* For uniprocessor GICs these RAZ/WI */
             res = 0;
         } else {
@@ -863,7 +863,7 @@ static void gic_dist_writeb(void *opaque, hwaddr offset,
         /* Interrupt CPU Target. RAZ/WI on uniprocessor GICs, with the
          * annoying exception of the 11MPCore's GIC.
          */
-        if (s->num_cpu != 1 || s->revision == REV_11MPCORE) {
+        if (NUM_CPU(s) != 1 || s->revision == REV_11MPCORE) {
             irq = (offset - 0x800) + GIC_BASE_IRQ;
             if (irq >= s->num_irq) {
                 goto bad_reg;
-- 
2.4.3