Re: [Qemu-arm] [PATCH 1/2] arm_mptimer: add watchdog mode support

[Peter Crosthwaite]

On Wed, Dec 9, 2015 at 2:26 AM, Rabin Vincent <address@hidden> wrote:
> Add support for the watchdog mode of the MPTimer.
>
> Signed-off-by: Rabin Vincent <address@hidden>
> ---
>  hw/timer/arm_mptimer.c         |   49 
> ++++++++++++++++++++++++++++++++++++----
>  include/hw/timer/arm_mptimer.h |    4 ++++
>  2 files changed, 49 insertions(+), 4 deletions(-)
>
> diff --git a/hw/timer/arm_mptimer.c b/hw/timer/arm_mptimer.c
> index 3e59c2a..2be4551 100644
> --- a/hw/timer/arm_mptimer.c
> +++ b/hw/timer/arm_mptimer.c
> @@ -21,8 +21,11 @@
>
>  #include "hw/timer/arm_mptimer.h"
>  #include "qemu/timer.h"
> +#include "sysemu/sysemu.h"
>  #include "qom/cpu.h"
>
> +#define TWD_CONTROL_WDOG_MODE   (1 << 3)
> +
>  /* This device implements the per-cpu private timer and watchdog block
>   * which is used in both the ARM11MPCore and Cortex-A9MP.
>   */
> @@ -38,7 +41,12 @@ static inline int get_current_cpu(ARMMPTimerState *s)
>
>  static inline void timerblock_update_irq(TimerBlock *tb)
>  {
> -    qemu_set_irq(tb->irq, tb->status && (tb->control & 4));
> +    if ((tb->control & TWD_CONTROL_WDOG_MODE) && tb->status) {
> +        qemu_log_mask(CPU_LOG_RESET, "MPCore Watchdog Reset\n");
> +        qemu_system_reset_request();

The actual consequences of a watchdog timeout are a SoC or board level
thing. The WDT (and MPCore) can only create the signal while the
instantiator of the SoC has to act on it for system level reset
consequences. We should match that. There was a similar thread with
Michael Davidsaver and the ARMv7M reset semantics:

https://lists.gnu.org/archive/html/qemu-devel/2015-10/msg02047.html

Regards,
Peter

> +    } else {
> +        qemu_set_irq(tb->irq, tb->status && (tb->control & 4));
> +    }
>  }
>