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[Qemu-arm] [PATCH 0/7] Fix some more EL3 things and enable EL3 for AArch
From: |
Peter Maydell |
Subject: |
[Qemu-arm] [PATCH 0/7] Fix some more EL3 things and enable EL3 for AArch64 |
Date: |
Wed, 3 Feb 2016 13:38:34 +0000 |
This series fixes a couple more minor EL3 related missing parts,
and then turns on EL3 for AArch64 CPUs. The minor fixed things are:
* implement MDCR_EL3 and SDCR
* trap Secure EL1 accesses to SCR and MVBAR to EL3
* add EL3 support to the code that decides whether to generate
debug exceptions
* fix corner cases in our NSACR handling
To do the NSACR fix I had to change the CPAccessFn API to take
an extra bool to tell the function if the access is a read or write.
The only major thing I know of that we're missing for 64-bit EL3
is that we need to go through the "EL3 configurable controls" section
of the ARM ARM to make sure we trap on the right things. But
(a) I expect we're missing some for 32-bit as well and (b) this
is enough to run some real-world EL3 code (ARM Trusted Firmware
and OP-TEE), so it makes sense to me to turn on EL3 now.
thanks
-- PMM
Peter Maydell (7):
target-arm: Fix typo in comment in arm_is_secure_below_el3()
target-arm: Implement MDCR_EL3 and SDCR
target-arm: Use access_trap_aa32s_el1() for SCR and MVBAR
target-arm: Update arm_generate_debug_exceptions() to handle EL2/EL3
target-arm: Add isread parameter to CPAccessFns
target-arm: Implement NSACR trapping behaviour
target-arm: Enable EL3 for Cortex-A53 and Cortex-A57
target-arm/cpu.h | 55 +++++++++++++--
target-arm/cpu64.c | 2 +
target-arm/helper.c | 171 ++++++++++++++++++++++++++++++++++++---------
target-arm/helper.h | 2 +-
target-arm/op_helper.c | 5 +-
target-arm/translate-a64.c | 6 +-
target-arm/translate.c | 7 +-
7 files changed, 200 insertions(+), 48 deletions(-)
--
1.9.1
- [Qemu-arm] [PATCH 0/7] Fix some more EL3 things and enable EL3 for AArch64,
Peter Maydell <=