[Qemu-arm] [PATCH v2 0/2] Implement MDCR_EL3.TPM and MDCR_EL2.TPM traps

[Peter Maydell]

This patchset implements the MDCR_EL3 and MDCR_EL2 trap bits
to trap the performance monitor registers.

Patch 2 is the same as I sent out earlier today as a standalone
patch. Patch 1 fixes a couple of bugs in our SDCR handling, and
in particular imposes a mask so that if a guest has booted with
EL3 in AArch32 then it cannot set bits like TPM which are RES0
for the 32-bit version of the register.

Peter Maydell (2):
  target-arm: Fix handling of SDCR for 32-bit code
  target-arm: Implement MDCR_EL3.TPM and MDCR_EL2.TPM traps

 target-arm/cpu.h    |  4 ++++
 target-arm/helper.c | 66 +++++++++++++++++++++++++++++++++++++++++------------
 2 files changed, 55 insertions(+), 15 deletions(-)

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1.9.1