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Re: [Qemu-arm] [Qemu-devel] [PATCH v5 6/9] ast2400: add SMC controllers
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From: |
Cédric Le Goater |
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Subject: |
Re: [Qemu-arm] [Qemu-devel] [PATCH v5 6/9] ast2400: add SMC controllers (FMC and SPI) |
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Date: |
Mon, 4 Jul 2016 08:58:42 +0200 |
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User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Icedove/45.1.0 |
Hello Marcin,
On 07/02/2016 07:00 PM, mar.krzeminski wrote:
>>
>> +
>> +/* CE Control Register */
>> +#define R_CE_CTRL (0x04 / 4)
>> +#define CTRL_EXTENDED4 4 /* 32 bit addressing for SPI */
>> +#define CTRL_EXTENDED3 3 /* 32 bit addressing for SPI */
>> +#define CTRL_EXTENDED2 2 /* 32 bit addressing for SPI */
>> +#define CTRL_EXTENDED1 1 /* 32 bit addressing for SPI */
>> +#define CTRL_EXTENDED0 0 /* 32 bit addressing for SPI */
> Hi
>
> Above comments does not say anything.
>
I suppose you mean that the names are confusing ?
The default setting for CE0 and CE1 is done with the hardware strapping
SCU70 register.
Thanks,
C.