Re: [Qemu-arm] [Qemu-devel] [PATCH v5 6/9] ast2400: add SMC controllers (FMC and SPI)

[Marcin Krzemiński]

2016-07-04 8:58 GMT+02:00 Cédric Le Goater <address@hidden>:

Hello Marcin,

On 07/02/2016 07:00 PM, mar.krzeminski wrote:
>>
>> +
>> +/* CE Control Register */
>> +#define R_CE_CTRL            (0x04 / 4)
>> +#define   CTRL_EXTENDED4       4  /* 32 bit addressing for SPI */
>> +#define   CTRL_EXTENDED3       3  /* 32 bit addressing for SPI */
>> +#define   CTRL_EXTENDED2       2  /* 32 bit addressing for SPI */
>> +#define   CTRL_EXTENDED1       1  /* 32 bit addressing for SPI */
>> +#define   CTRL_EXTENDED0       0  /* 32 bit addressing for SPI */
> Hi
>
> Above comments does not say anything.
>

I suppose you mean that the names are confusing ?

The default setting for CE0 and CE1 is done with the hardware strapping
SCU70 register.

Yes, is hard to say what does it mean and what it does (at least for me). This is a minor.

Thanks,

Marcin 

Thanks,

C.