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Re: [Qemu-arm] [Qemu-ppc] [PATCH 1/4] Pass generic CPUState to gen_inter
|
From: |
David Gibson |
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Subject: |
Re: [Qemu-arm] [Qemu-ppc] [PATCH 1/4] Pass generic CPUState to gen_intermediate_code() |
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Date: |
Mon, 18 Jul 2016 11:39:29 +1000 |
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User-agent: |
Mutt/1.6.1 (2016-04-27) |
On Fri, Jul 15, 2016 at 06:12:05PM +0200, Lluís Vilanova wrote:
> Needed to implement a target-agnostic gen_intermediate_code() in the
> future.
>
> Signed-off-by: Lluís Vilanova <address@hidden>
> ---
> include/exec/exec-all.h | 2 +-
> target-alpha/translate.c | 11 +++++------
> target-arm/translate.c | 24 ++++++++++++------------
> target-cris/translate.c | 17 ++++++++---------
> target-i386/translate.c | 13 ++++++-------
> target-lm32/translate.c | 22 +++++++++++-----------
> target-m68k/translate.c | 15 +++++++--------
> target-microblaze/translate.c | 24 ++++++++++++------------
> target-mips/translate.c | 15 +++++++--------
> target-moxie/translate.c | 14 +++++++-------
> target-openrisc/translate.c | 24 ++++++++++++------------
> target-ppc/translate.c | 15 +++++++--------
> target-s390x/translate.c | 13 ++++++-------
> target-sh4/translate.c | 15 +++++++--------
> target-sparc/translate.c | 11 +++++------
> target-tilegx/translate.c | 7 +++----
> target-tricore/translate.c | 9 ++++-----
> target-unicore32/translate.c | 17 ++++++++---------
> target-xtensa/translate.c | 13 ++++++-------
> translate-all.c | 2 +-
> 20 files changed, 135 insertions(+), 148 deletions(-)
target-ppc portion
Reviewed-by: David Gibson <address@hidden>
> diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
> index 7362095..06c2400 100644
> --- a/include/exec/exec-all.h
> +++ b/include/exec/exec-all.h
> @@ -66,7 +66,7 @@ typedef struct TranslationBlock TranslationBlock;
>
> #include "qemu/log.h"
>
> -void gen_intermediate_code(CPUArchState *env, struct TranslationBlock *tb);
> +void gen_intermediate_code(CPUState *env, struct TranslationBlock *tb);
> void restore_state_to_opc(CPUArchState *env, struct TranslationBlock *tb,
> target_ulong *data);
>
> diff --git a/target-alpha/translate.c b/target-alpha/translate.c
> index 5b86992..faeccf8 100644
> --- a/target-alpha/translate.c
> +++ b/target-alpha/translate.c
> @@ -2860,10 +2860,9 @@ static ExitStatus translate_one(DisasContext *ctx,
> uint32_t insn)
> return ret;
> }
>
> -void gen_intermediate_code(CPUAlphaState *env, struct TranslationBlock *tb)
> +void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb)
> {
> - AlphaCPU *cpu = alpha_env_get_cpu(env);
> - CPUState *cs = CPU(cpu);
> + CPUAlphaState *env = cpu->env_ptr;
> DisasContext ctx, *ctxp = &ctx;
> target_ulong pc_start;
> target_ulong pc_mask;
> @@ -2878,7 +2877,7 @@ void gen_intermediate_code(CPUAlphaState *env, struct
> TranslationBlock *tb)
> ctx.pc = pc_start;
> ctx.mem_idx = cpu_mmu_index(env, false);
> ctx.implver = env->implver;
> - ctx.singlestep_enabled = cs->singlestep_enabled;
> + ctx.singlestep_enabled = cpu->singlestep_enabled;
>
> #ifdef CONFIG_USER_ONLY
> ctx.ir = cpu_std_ir;
> @@ -2917,7 +2916,7 @@ void gen_intermediate_code(CPUAlphaState *env, struct
> TranslationBlock *tb)
> tcg_gen_insn_start(ctx.pc);
> num_insns++;
>
> - if (unlikely(cpu_breakpoint_test(cs, ctx.pc, BP_ANY))) {
> + if (unlikely(cpu_breakpoint_test(cpu, ctx.pc, BP_ANY))) {
> ret = gen_excp(&ctx, EXCP_DEBUG, 0);
> /* The address covered by the breakpoint must be included in
> [tb->pc, tb->pc + tb->size) in order to for it to be
> @@ -2991,7 +2990,7 @@ void gen_intermediate_code(CPUAlphaState *env, struct
> TranslationBlock *tb)
> #ifdef DEBUG_DISAS
> if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
> qemu_log("IN: %s\n", lookup_symbol(pc_start));
> - log_target_disas(cs, pc_start, ctx.pc - pc_start, 1);
> + log_target_disas(cpu, pc_start, ctx.pc - pc_start, 1);
> qemu_log("\n");
> }
> #endif
> diff --git a/target-arm/translate.c b/target-arm/translate.c
> index 940ec8d..837ceda 100644
> --- a/target-arm/translate.c
> +++ b/target-arm/translate.c
> @@ -11587,10 +11587,10 @@ static bool insn_crosses_page(CPUARMState *env,
> DisasContext *s)
> }
>
> /* generate intermediate code for basic block 'tb'. */
> -void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb)
> +void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb)
> {
> - ARMCPU *cpu = arm_env_get_cpu(env);
> - CPUState *cs = CPU(cpu);
> + CPUARMState *env = cpu->env_ptr;
> + ARMCPU *arm_cpu = arm_env_get_cpu(env);
> DisasContext dc1, *dc = &dc1;
> target_ulong pc_start;
> target_ulong next_page_start;
> @@ -11604,7 +11604,7 @@ void gen_intermediate_code(CPUARMState *env,
> TranslationBlock *tb)
> * the A32/T32 complexity to do with conditional execution/IT blocks/etc.
> */
> if (ARM_TBFLAG_AARCH64_STATE(tb->flags)) {
> - gen_intermediate_code_a64(cpu, tb);
> + gen_intermediate_code_a64(arm_cpu, tb);
> return;
> }
>
> @@ -11614,7 +11614,7 @@ void gen_intermediate_code(CPUARMState *env,
> TranslationBlock *tb)
>
> dc->is_jmp = DISAS_NEXT;
> dc->pc = pc_start;
> - dc->singlestep_enabled = cs->singlestep_enabled;
> + dc->singlestep_enabled = cpu->singlestep_enabled;
> dc->condjmp = 0;
>
> dc->aarch64 = 0;
> @@ -11639,7 +11639,7 @@ void gen_intermediate_code(CPUARMState *env,
> TranslationBlock *tb)
> dc->vec_len = ARM_TBFLAG_VECLEN(tb->flags);
> dc->vec_stride = ARM_TBFLAG_VECSTRIDE(tb->flags);
> dc->c15_cpar = ARM_TBFLAG_XSCALE_CPAR(tb->flags);
> - dc->cp_regs = cpu->cp_regs;
> + dc->cp_regs = arm_cpu->cp_regs;
> dc->features = env->features;
>
> /* Single step state. The code-generation logic here is:
> @@ -11746,9 +11746,9 @@ void gen_intermediate_code(CPUARMState *env,
> TranslationBlock *tb)
> }
> #endif
>
> - if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {
> + if (unlikely(!QTAILQ_EMPTY(&cpu->breakpoints))) {
> CPUBreakpoint *bp;
> - QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
> + QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) {
> if (bp->pc == dc->pc) {
> if (bp->flags & BP_CPU) {
> gen_set_condexec(dc);
> @@ -11838,7 +11838,7 @@ void gen_intermediate_code(CPUARMState *env,
> TranslationBlock *tb)
> ((dc->pc >= next_page_start - 3) && insn_crosses_page(env, dc));
>
> } while (!dc->is_jmp && !tcg_op_buf_full() &&
> - !cs->singlestep_enabled &&
> + !cpu->singlestep_enabled &&
> !singlestep &&
> !dc->ss_active &&
> !end_of_page &&
> @@ -11848,7 +11848,7 @@ void gen_intermediate_code(CPUARMState *env,
> TranslationBlock *tb)
> if (dc->condjmp) {
> /* FIXME: This can theoretically happen with self-modifying
> code. */
> - cpu_abort(cs, "IO on conditional branch instruction");
> + cpu_abort(cpu, "IO on conditional branch instruction");
> }
> gen_io_end();
> }
> @@ -11856,7 +11856,7 @@ void gen_intermediate_code(CPUARMState *env,
> TranslationBlock *tb)
> /* At this stage dc->condjmp will only be set when the skipped
> instruction was a conditional branch or trap, and the PC has
> already been written. */
> - if (unlikely(cs->singlestep_enabled || dc->ss_active)) {
> + if (unlikely(cpu->singlestep_enabled || dc->ss_active)) {
> /* Unconditional and "condition passed" instruction codepath. */
> gen_set_condexec(dc);
> switch (dc->is_jmp) {
> @@ -11962,7 +11962,7 @@ done_generating:
> qemu_log_in_addr_range(pc_start)) {
> qemu_log("----------------\n");
> qemu_log("IN: %s\n", lookup_symbol(pc_start));
> - log_target_disas(cs, pc_start, dc->pc - pc_start,
> + log_target_disas(cpu, pc_start, dc->pc - pc_start,
> dc->thumb | (dc->sctlr_b << 1));
> qemu_log("\n");
> }
> diff --git a/target-cris/translate.c b/target-cris/translate.c
> index a73176c..90d63c1 100644
> --- a/target-cris/translate.c
> +++ b/target-cris/translate.c
> @@ -3071,10 +3071,9 @@ static unsigned int crisv32_decoder(CPUCRISState *env,
> DisasContext *dc)
> */
>
> /* generate intermediate code for basic block 'tb'. */
> -void gen_intermediate_code(CPUCRISState *env, struct TranslationBlock *tb)
> +void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb)
> {
> - CRISCPU *cpu = cris_env_get_cpu(env);
> - CPUState *cs = CPU(cpu);
> + CPUCRISState *env = cpu->env_ptr;
> uint32_t pc_start;
> unsigned int insn_len;
> struct DisasContext ctx;
> @@ -3096,13 +3095,13 @@ void gen_intermediate_code(CPUCRISState *env, struct
> TranslationBlock *tb)
> * delayslot, like in real hw.
> */
> pc_start = tb->pc & ~1;
> - dc->cpu = cpu;
> + dc->cpu = cris_env_get_cpu(env);
> dc->tb = tb;
>
> dc->is_jmp = DISAS_NEXT;
> dc->ppc = pc_start;
> dc->pc = pc_start;
> - dc->singlestep_enabled = cs->singlestep_enabled;
> + dc->singlestep_enabled = cpu->singlestep_enabled;
> dc->flags_uptodate = 1;
> dc->flagx_known = 1;
> dc->flags_x = tb->flags & X_FLAG;
> @@ -3165,7 +3164,7 @@ void gen_intermediate_code(CPUCRISState *env, struct
> TranslationBlock *tb)
> ? dc->ppc | 1 : dc->pc);
> num_insns++;
>
> - if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) {
> + if (unlikely(cpu_breakpoint_test(cpu, dc->pc, BP_ANY))) {
> cris_evaluate_flags(dc);
> tcg_gen_movi_tl(env_pc, dc->pc);
> t_gen_raise_exception(EXCP_DEBUG);
> @@ -3239,7 +3238,7 @@ void gen_intermediate_code(CPUCRISState *env, struct
> TranslationBlock *tb)
>
> /* If we are rexecuting a branch due to exceptions on
> delay slots dont break. */
> - if (!(tb->pc & 1) && cs->singlestep_enabled) {
> + if (!(tb->pc & 1) && cpu->singlestep_enabled) {
> break;
> }
> } while (!dc->is_jmp && !dc->cpustate_changed
> @@ -3272,7 +3271,7 @@ void gen_intermediate_code(CPUCRISState *env, struct
> TranslationBlock *tb)
>
> cris_evaluate_flags(dc);
>
> - if (unlikely(cs->singlestep_enabled)) {
> + if (unlikely(cpu->singlestep_enabled)) {
> if (dc->is_jmp == DISAS_NEXT) {
> tcg_gen_movi_tl(env_pc, npc);
> }
> @@ -3303,7 +3302,7 @@ void gen_intermediate_code(CPUCRISState *env, struct
> TranslationBlock *tb)
> #ifdef DEBUG_DISAS
> #if !DISAS_CRIS
> if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
> - log_target_disas(cs, pc_start, dc->pc - pc_start,
> + log_target_disas(cpu, pc_start, dc->pc - pc_start,
> env->pregs[PR_VR]);
> qemu_log("\nisize=%d osize=%d\n",
> dc->pc - pc_start, tcg_op_buf_count());
> diff --git a/target-i386/translate.c b/target-i386/translate.c
> index 1a1214d..68e2593 100644
> --- a/target-i386/translate.c
> +++ b/target-i386/translate.c
> @@ -8172,10 +8172,9 @@ void tcg_x86_init(void)
> }
>
> /* generate intermediate code for basic block 'tb'. */
> -void gen_intermediate_code(CPUX86State *env, TranslationBlock *tb)
> +void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb)
> {
> - X86CPU *cpu = x86_env_get_cpu(env);
> - CPUState *cs = CPU(cpu);
> + CPUX86State *env = cpu->env_ptr;
> DisasContext dc1, *dc = &dc1;
> target_ulong pc_ptr;
> uint64_t flags;
> @@ -8198,7 +8197,7 @@ void gen_intermediate_code(CPUX86State *env,
> TranslationBlock *tb)
> dc->cpl = (flags >> HF_CPL_SHIFT) & 3;
> dc->iopl = (flags >> IOPL_SHIFT) & 3;
> dc->tf = (flags >> TF_SHIFT) & 1;
> - dc->singlestep_enabled = cs->singlestep_enabled;
> + dc->singlestep_enabled = cpu->singlestep_enabled;
> dc->cc_op = CC_OP_DYNAMIC;
> dc->cc_op_dirty = false;
> dc->cs_base = cs_base;
> @@ -8220,7 +8219,7 @@ void gen_intermediate_code(CPUX86State *env,
> TranslationBlock *tb)
> dc->code64 = (flags >> HF_CS64_SHIFT) & 1;
> #endif
> dc->flags = flags;
> - dc->jmp_opt = !(dc->tf || cs->singlestep_enabled ||
> + dc->jmp_opt = !(dc->tf || cpu->singlestep_enabled ||
> (flags & HF_INHIBIT_IRQ_MASK)
> #ifndef CONFIG_SOFTMMU
> || (flags & HF_SOFTMMU_MASK)
> @@ -8273,7 +8272,7 @@ void gen_intermediate_code(CPUX86State *env,
> TranslationBlock *tb)
> num_insns++;
>
> /* If RF is set, suppress an internally generated breakpoint. */
> - if (unlikely(cpu_breakpoint_test(cs, pc_ptr,
> + if (unlikely(cpu_breakpoint_test(cpu, pc_ptr,
> tb->flags & HF_RF_MASK
> ? BP_GDB : BP_ANY))) {
> gen_debug(dc, pc_ptr - dc->cs_base);
> @@ -8347,7 +8346,7 @@ done_generating:
> else
> #endif
> disas_flags = !dc->code32;
> - log_target_disas(cs, pc_start, pc_ptr - pc_start, disas_flags);
> + log_target_disas(cpu, pc_start, pc_ptr - pc_start, disas_flags);
> qemu_log("\n");
> }
> #endif
> diff --git a/target-lm32/translate.c b/target-lm32/translate.c
> index 256a51f..9721d31 100644
> --- a/target-lm32/translate.c
> +++ b/target-lm32/translate.c
> @@ -1035,10 +1035,10 @@ static inline void decode(DisasContext *dc, uint32_t
> ir)
> }
>
> /* generate intermediate code for basic block 'tb'. */
> -void gen_intermediate_code(CPULM32State *env, struct TranslationBlock *tb)
> +void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb)
> {
> - LM32CPU *cpu = lm32_env_get_cpu(env);
> - CPUState *cs = CPU(cpu);
> + CPULM32State *env = cpu->env_ptr;
> + LM32CPU *lm32_cpu = lm32_env_get_cpu(env);
> struct DisasContext ctx, *dc = &ctx;
> uint32_t pc_start;
> uint32_t next_page_start;
> @@ -1046,14 +1046,14 @@ void gen_intermediate_code(CPULM32State *env, struct
> TranslationBlock *tb)
> int max_insns;
>
> pc_start = tb->pc;
> - dc->features = cpu->features;
> - dc->num_breakpoints = cpu->num_breakpoints;
> - dc->num_watchpoints = cpu->num_watchpoints;
> + dc->features = lm32_cpu->features;
> + dc->num_breakpoints = lm32_cpu->num_breakpoints;
> + dc->num_watchpoints = lm32_cpu->num_watchpoints;
> dc->tb = tb;
>
> dc->is_jmp = DISAS_NEXT;
> dc->pc = pc_start;
> - dc->singlestep_enabled = cs->singlestep_enabled;
> + dc->singlestep_enabled = cpu->singlestep_enabled;
>
> if (pc_start & 3) {
> qemu_log_mask(LOG_GUEST_ERROR,
> @@ -1076,7 +1076,7 @@ void gen_intermediate_code(CPULM32State *env, struct
> TranslationBlock *tb)
> tcg_gen_insn_start(dc->pc);
> num_insns++;
>
> - if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) {
> + if (unlikely(cpu_breakpoint_test(cpu, dc->pc, BP_ANY))) {
> tcg_gen_movi_tl(cpu_pc, dc->pc);
> t_gen_raise_exception(dc, EXCP_DEBUG);
> dc->is_jmp = DISAS_UPDATE;
> @@ -1099,7 +1099,7 @@ void gen_intermediate_code(CPULM32State *env, struct
> TranslationBlock *tb)
> dc->pc += 4;
> } while (!dc->is_jmp
> && !tcg_op_buf_full()
> - && !cs->singlestep_enabled
> + && !cpu->singlestep_enabled
> && !singlestep
> && (dc->pc < next_page_start)
> && num_insns < max_insns);
> @@ -1108,7 +1108,7 @@ void gen_intermediate_code(CPULM32State *env, struct
> TranslationBlock *tb)
> gen_io_end();
> }
>
> - if (unlikely(cs->singlestep_enabled)) {
> + if (unlikely(cpu->singlestep_enabled)) {
> if (dc->is_jmp == DISAS_NEXT) {
> tcg_gen_movi_tl(cpu_pc, dc->pc);
> }
> @@ -1139,7 +1139,7 @@ void gen_intermediate_code(CPULM32State *env, struct
> TranslationBlock *tb)
> #ifdef DEBUG_DISAS
> if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
> qemu_log("\n");
> - log_target_disas(cs, pc_start, dc->pc - pc_start, 0);
> + log_target_disas(cpu, pc_start, dc->pc - pc_start, 0);
> qemu_log("\nisize=%d osize=%d\n",
> dc->pc - pc_start, tcg_op_buf_count());
> }
> diff --git a/target-m68k/translate.c b/target-m68k/translate.c
> index 7560c3a..a3aaef2 100644
> --- a/target-m68k/translate.c
> +++ b/target-m68k/translate.c
> @@ -2968,10 +2968,9 @@ static void disas_m68k_insn(CPUM68KState * env,
> DisasContext *s)
> }
>
> /* generate intermediate code for basic block 'tb'. */
> -void gen_intermediate_code(CPUM68KState *env, TranslationBlock *tb)
> +void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb)
> {
> - M68kCPU *cpu = m68k_env_get_cpu(env);
> - CPUState *cs = CPU(cpu);
> + CPUM68KState *env = cpu->env_ptr;
> DisasContext dc1, *dc = &dc1;
> target_ulong pc_start;
> int pc_offset;
> @@ -2987,7 +2986,7 @@ void gen_intermediate_code(CPUM68KState *env,
> TranslationBlock *tb)
> dc->is_jmp = DISAS_NEXT;
> dc->pc = pc_start;
> dc->cc_op = CC_OP_DYNAMIC;
> - dc->singlestep_enabled = cs->singlestep_enabled;
> + dc->singlestep_enabled = cpu->singlestep_enabled;
> dc->fpcr = env->fpcr;
> dc->user = (env->sr & SR_S) == 0;
> dc->done_mac = 0;
> @@ -3007,7 +3006,7 @@ void gen_intermediate_code(CPUM68KState *env,
> TranslationBlock *tb)
> tcg_gen_insn_start(dc->pc);
> num_insns++;
>
> - if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) {
> + if (unlikely(cpu_breakpoint_test(cpu, dc->pc, BP_ANY))) {
> gen_exception(dc, dc->pc, EXCP_DEBUG);
> dc->is_jmp = DISAS_JUMP;
> /* The address covered by the breakpoint must be included in
> @@ -3025,14 +3024,14 @@ void gen_intermediate_code(CPUM68KState *env,
> TranslationBlock *tb)
> dc->insn_pc = dc->pc;
> disas_m68k_insn(env, dc);
> } while (!dc->is_jmp && !tcg_op_buf_full() &&
> - !cs->singlestep_enabled &&
> + !cpu->singlestep_enabled &&
> !singlestep &&
> (pc_offset) < (TARGET_PAGE_SIZE - 32) &&
> num_insns < max_insns);
>
> if (tb->cflags & CF_LAST_IO)
> gen_io_end();
> - if (unlikely(cs->singlestep_enabled)) {
> + if (unlikely(cpu->singlestep_enabled)) {
> /* Make sure the pc is updated, and raise a debug exception. */
> if (!dc->is_jmp) {
> gen_flush_cc_op(dc);
> @@ -3063,7 +3062,7 @@ void gen_intermediate_code(CPUM68KState *env,
> TranslationBlock *tb)
> if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
> qemu_log("----------------\n");
> qemu_log("IN: %s\n", lookup_symbol(pc_start));
> - log_target_disas(cs, pc_start, dc->pc - pc_start, 0);
> + log_target_disas(cpu, pc_start, dc->pc - pc_start, 0);
> qemu_log("\n");
> }
> #endif
> diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c
> index f944965..201e9fd 100644
> --- a/target-microblaze/translate.c
> +++ b/target-microblaze/translate.c
> @@ -1629,10 +1629,10 @@ static inline void decode(DisasContext *dc, uint32_t
> ir)
> }
>
> /* generate intermediate code for basic block 'tb'. */
> -void gen_intermediate_code(CPUMBState *env, struct TranslationBlock *tb)
> +void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb)
> {
> - MicroBlazeCPU *cpu = mb_env_get_cpu(env);
> - CPUState *cs = CPU(cpu);
> + CPUMBState *env = cpu->env_ptr;
> + MicroBlazeCPU *mb_cpu = mb_env_get_cpu(env);
> uint32_t pc_start;
> struct DisasContext ctx;
> struct DisasContext *dc = &ctx;
> @@ -1642,7 +1642,7 @@ void gen_intermediate_code(CPUMBState *env, struct
> TranslationBlock *tb)
> int max_insns;
>
> pc_start = tb->pc;
> - dc->cpu = cpu;
> + dc->cpu = mb_cpu;
> dc->tb = tb;
> org_flags = dc->synced_flags = dc->tb_flags = tb->flags;
>
> @@ -1653,19 +1653,19 @@ void gen_intermediate_code(CPUMBState *env, struct
> TranslationBlock *tb)
> dc->jmp = JMP_INDIRECT;
> }
> dc->pc = pc_start;
> - dc->singlestep_enabled = cs->singlestep_enabled;
> + dc->singlestep_enabled = cpu->singlestep_enabled;
> dc->cpustate_changed = 0;
> dc->abort_at_next_insn = 0;
> dc->nr_nops = 0;
>
> if (pc_start & 3) {
> - cpu_abort(cs, "Microblaze: unaligned PC=%x\n", pc_start);
> + cpu_abort(cpu, "Microblaze: unaligned PC=%x\n", pc_start);
> }
>
> if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
> #if !SIM_COMPAT
> qemu_log("--------------\n");
> - log_cpu_state(CPU(cpu), 0);
> + log_cpu_state(CPU(mb_cpu), 0);
> #endif
> }
>
> @@ -1692,7 +1692,7 @@ void gen_intermediate_code(CPUMBState *env, struct
> TranslationBlock *tb)
> }
> #endif
>
> - if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) {
> + if (unlikely(cpu_breakpoint_test(cpu, dc->pc, BP_ANY))) {
> t_gen_raise_exception(dc, EXCP_DEBUG);
> dc->is_jmp = DISAS_UPDATE;
> /* The address covered by the breakpoint must be included in
> @@ -1749,7 +1749,7 @@ void gen_intermediate_code(CPUMBState *env, struct
> TranslationBlock *tb)
> break;
> }
> }
> - if (cs->singlestep_enabled) {
> + if (cpu->singlestep_enabled) {
> break;
> }
> } while (!dc->is_jmp && !dc->cpustate_changed
> @@ -1770,7 +1770,7 @@ void gen_intermediate_code(CPUMBState *env, struct
> TranslationBlock *tb)
>
> if (tb->cflags & CF_LAST_IO)
> gen_io_end();
> - /* Force an update if the per-tb cpu state has changed. */
> + /* Force an update if the per-tb mb_cpu state has changed. */
> if (dc->is_jmp == DISAS_NEXT
> && (dc->cpustate_changed || org_flags != dc->tb_flags)) {
> dc->is_jmp = DISAS_UPDATE;
> @@ -1778,7 +1778,7 @@ void gen_intermediate_code(CPUMBState *env, struct
> TranslationBlock *tb)
> }
> t_sync_flags(dc);
>
> - if (unlikely(cs->singlestep_enabled)) {
> + if (unlikely(cpu->singlestep_enabled)) {
> TCGv_i32 tmp = tcg_const_i32(EXCP_DEBUG);
>
> if (dc->is_jmp != DISAS_JUMP) {
> @@ -1813,7 +1813,7 @@ void gen_intermediate_code(CPUMBState *env, struct
> TranslationBlock *tb)
> if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
> qemu_log("\n");
> #if DISAS_GNU
> - log_target_disas(cs, pc_start, dc->pc - pc_start, 0);
> + log_target_disas(cpu, pc_start, dc->pc - pc_start, 0);
> #endif
> qemu_log("\nisize=%d osize=%d\n",
> dc->pc - pc_start, tcg_op_buf_count());
> diff --git a/target-mips/translate.c b/target-mips/translate.c
> index a3a05ec..2c2f14a 100644
> --- a/target-mips/translate.c
> +++ b/target-mips/translate.c
> @@ -19737,10 +19737,9 @@ static void decode_opc(CPUMIPSState *env,
> DisasContext *ctx)
> }
> }
>
> -void gen_intermediate_code(CPUMIPSState *env, struct TranslationBlock *tb)
> +void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb)
> {
> - MIPSCPU *cpu = mips_env_get_cpu(env);
> - CPUState *cs = CPU(cpu);
> + CPUMIPSState *env = cpu->env_ptr;
> DisasContext ctx;
> target_ulong pc_start;
> target_ulong next_page_start;
> @@ -19753,7 +19752,7 @@ void gen_intermediate_code(CPUMIPSState *env, struct
> TranslationBlock *tb)
> next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
> ctx.pc = pc_start;
> ctx.saved_pc = -1;
> - ctx.singlestep_enabled = cs->singlestep_enabled;
> + ctx.singlestep_enabled = cpu->singlestep_enabled;
> ctx.insn_flags = env->insn_flags;
> ctx.CP0_Config1 = env->CP0_Config1;
> ctx.tb = tb;
> @@ -19798,7 +19797,7 @@ void gen_intermediate_code(CPUMIPSState *env, struct
> TranslationBlock *tb)
> tcg_gen_insn_start(ctx.pc, ctx.hflags & MIPS_HFLAG_BMASK,
> ctx.btarget);
> num_insns++;
>
> - if (unlikely(cpu_breakpoint_test(cs, ctx.pc, BP_ANY))) {
> + if (unlikely(cpu_breakpoint_test(cpu, ctx.pc, BP_ANY))) {
> save_cpu_state(&ctx, 1);
> ctx.bstate = BS_BRANCH;
> gen_helper_raise_exception_debug(cpu_env);
> @@ -19853,7 +19852,7 @@ void gen_intermediate_code(CPUMIPSState *env, struct
> TranslationBlock *tb)
> This is what GDB expects and is consistent with what the
> hardware does (e.g. if a delay slot instruction faults, the
> reported PC is the PC of the branch). */
> - if (cs->singlestep_enabled && (ctx.hflags & MIPS_HFLAG_BMASK) == 0) {
> + if (cpu->singlestep_enabled && (ctx.hflags & MIPS_HFLAG_BMASK) == 0)
> {
> break;
> }
>
> @@ -19874,7 +19873,7 @@ void gen_intermediate_code(CPUMIPSState *env, struct
> TranslationBlock *tb)
> if (tb->cflags & CF_LAST_IO) {
> gen_io_end();
> }
> - if (cs->singlestep_enabled && ctx.bstate != BS_BRANCH) {
> + if (cpu->singlestep_enabled && ctx.bstate != BS_BRANCH) {
> save_cpu_state(&ctx, ctx.bstate != BS_EXCP);
> gen_helper_raise_exception_debug(cpu_env);
> } else {
> @@ -19904,7 +19903,7 @@ done_generating:
> LOG_DISAS("\n");
> if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
> qemu_log("IN: %s\n", lookup_symbol(pc_start));
> - log_target_disas(cs, pc_start, ctx.pc - pc_start, 0);
> + log_target_disas(cpu, pc_start, ctx.pc - pc_start, 0);
> qemu_log("\n");
> }
> #endif
> diff --git a/target-moxie/translate.c b/target-moxie/translate.c
> index a437e2a..19f7453 100644
> --- a/target-moxie/translate.c
> +++ b/target-moxie/translate.c
> @@ -812,10 +812,10 @@ static int decode_opc(MoxieCPU *cpu, DisasContext *ctx)
> }
>
> /* generate intermediate code for basic block 'tb'. */
> -void gen_intermediate_code(CPUMoxieState *env, struct TranslationBlock *tb)
> +void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb)
> {
> - MoxieCPU *cpu = moxie_env_get_cpu(env);
> - CPUState *cs = CPU(cpu);
> + CPUMoxieState *env = cpu->env_ptr;
> + MoxieCPU *moxie_cpu = moxie_env_get_cpu(env);
> DisasContext ctx;
> target_ulong pc_start;
> int num_insns, max_insns;
> @@ -841,7 +841,7 @@ void gen_intermediate_code(CPUMoxieState *env, struct
> TranslationBlock *tb)
> tcg_gen_insn_start(ctx.pc);
> num_insns++;
>
> - if (unlikely(cpu_breakpoint_test(cs, ctx.pc, BP_ANY))) {
> + if (unlikely(cpu_breakpoint_test(cpu, ctx.pc, BP_ANY))) {
> tcg_gen_movi_i32(cpu_pc, ctx.pc);
> gen_helper_debug(cpu_env);
> ctx.bstate = BS_EXCP;
> @@ -854,12 +854,12 @@ void gen_intermediate_code(CPUMoxieState *env, struct
> TranslationBlock *tb)
> }
>
> ctx.opcode = cpu_lduw_code(env, ctx.pc);
> - ctx.pc += decode_opc(cpu, &ctx);
> + ctx.pc += decode_opc(moxie_cpu, &ctx);
>
> if (num_insns >= max_insns) {
> break;
> }
> - if (cs->singlestep_enabled) {
> + if (cpu->singlestep_enabled) {
> break;
> }
> if ((ctx.pc & (TARGET_PAGE_SIZE - 1)) == 0) {
> @@ -867,7 +867,7 @@ void gen_intermediate_code(CPUMoxieState *env, struct
> TranslationBlock *tb)
> }
> } while (ctx.bstate == BS_NONE && !tcg_op_buf_full());
>
> - if (cs->singlestep_enabled) {
> + if (cpu->singlestep_enabled) {
> tcg_gen_movi_tl(cpu_pc, ctx.pc);
> gen_helper_debug(cpu_env);
> } else {
> diff --git a/target-openrisc/translate.c b/target-openrisc/translate.c
> index 5d0ab44..b441625 100644
> --- a/target-openrisc/translate.c
> +++ b/target-openrisc/translate.c
> @@ -1619,10 +1619,10 @@ static void disas_openrisc_insn(DisasContext *dc,
> OpenRISCCPU *cpu)
> }
> }
>
> -void gen_intermediate_code(CPUOpenRISCState *env, struct TranslationBlock
> *tb)
> +void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb)
> {
> - OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
> - CPUState *cs = CPU(cpu);
> + CPUOpenRISCState *env = cpu->env_ptr;
> + OpenRISCCPU *or_cpu = openrisc_env_get_cpu(env);
> struct DisasContext ctx, *dc = &ctx;
> uint32_t pc_start;
> uint32_t next_page_start;
> @@ -1635,14 +1635,14 @@ void gen_intermediate_code(CPUOpenRISCState *env,
> struct TranslationBlock *tb)
> dc->is_jmp = DISAS_NEXT;
> dc->ppc = pc_start;
> dc->pc = pc_start;
> - dc->flags = cpu->env.cpucfgr;
> - dc->mem_idx = cpu_mmu_index(&cpu->env, false);
> + dc->flags = or_cpu->env.cpucfgr;
> + dc->mem_idx = cpu_mmu_index(&or_cpu->env, false);
> dc->synced_flags = dc->tb_flags = tb->flags;
> dc->delayed_branch = !!(dc->tb_flags & D_FLAG);
> - dc->singlestep_enabled = cs->singlestep_enabled;
> + dc->singlestep_enabled = cpu->singlestep_enabled;
> if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
> qemu_log("-----------------------------------------\n");
> - log_cpu_state(CPU(cpu), 0);
> + log_cpu_state(CPU(or_cpu), 0);
> }
>
> next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
> @@ -1662,7 +1662,7 @@ void gen_intermediate_code(CPUOpenRISCState *env,
> struct TranslationBlock *tb)
> tcg_gen_insn_start(dc->pc);
> num_insns++;
>
> - if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) {
> + if (unlikely(cpu_breakpoint_test(cpu, dc->pc, BP_ANY))) {
> tcg_gen_movi_tl(cpu_pc, dc->pc);
> gen_exception(dc, EXCP_DEBUG);
> dc->is_jmp = DISAS_UPDATE;
> @@ -1681,7 +1681,7 @@ void gen_intermediate_code(CPUOpenRISCState *env,
> struct TranslationBlock *tb)
> dc->npc = dc->pc + 4;
> tcg_gen_movi_tl(cpu_ppc, dc->ppc);
> tcg_gen_movi_tl(cpu_npc, dc->npc);
> - disas_openrisc_insn(dc, cpu);
> + disas_openrisc_insn(dc, or_cpu);
> dc->pc = dc->npc;
> /* delay slot */
> if (dc->delayed_branch) {
> @@ -1699,7 +1699,7 @@ void gen_intermediate_code(CPUOpenRISCState *env,
> struct TranslationBlock *tb)
> }
> } while (!dc->is_jmp
> && !tcg_op_buf_full()
> - && !cs->singlestep_enabled
> + && !cpu->singlestep_enabled
> && !singlestep
> && (dc->pc < next_page_start)
> && num_insns < max_insns);
> @@ -1711,7 +1711,7 @@ void gen_intermediate_code(CPUOpenRISCState *env,
> struct TranslationBlock *tb)
> dc->is_jmp = DISAS_UPDATE;
> tcg_gen_movi_tl(cpu_pc, dc->pc);
> }
> - if (unlikely(cs->singlestep_enabled)) {
> + if (unlikely(cpu->singlestep_enabled)) {
> if (dc->is_jmp == DISAS_NEXT) {
> tcg_gen_movi_tl(cpu_pc, dc->pc);
> }
> @@ -1743,7 +1743,7 @@ void gen_intermediate_code(CPUOpenRISCState *env,
> struct TranslationBlock *tb)
> #ifdef DEBUG_DISAS
> if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
> qemu_log("\n");
> - log_target_disas(cs, pc_start, dc->pc - pc_start, 0);
> + log_target_disas(cpu, pc_start, dc->pc - pc_start, 0);
> qemu_log("\nisize=%d osize=%d\n",
> dc->pc - pc_start, tcg_op_buf_count());
> }
> diff --git a/target-ppc/translate.c b/target-ppc/translate.c
> index b3860ec..bad896e 100644
> --- a/target-ppc/translate.c
> +++ b/target-ppc/translate.c
> @@ -11438,10 +11438,9 @@ void ppc_cpu_dump_statistics(CPUState *cs, FILE*f,
> }
>
>
> /*****************************************************************************/
> -void gen_intermediate_code(CPUPPCState *env, struct TranslationBlock *tb)
> +void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb)
> {
> - PowerPCCPU *cpu = ppc_env_get_cpu(env);
> - CPUState *cs = CPU(cpu);
> + CPUPPCState *env = cpu->env_ptr;
> DisasContext ctx, *ctxp = &ctx;
> opc_handler_t **table, *handler;
> target_ulong pc_start;
> @@ -11492,7 +11491,7 @@ void gen_intermediate_code(CPUPPCState *env, struct
> TranslationBlock *tb)
> ctx.singlestep_enabled = 0;
> if ((env->flags & POWERPC_FLAG_BE) && msr_be)
> ctx.singlestep_enabled |= CPU_BRANCH_STEP;
> - if (unlikely(cs->singlestep_enabled)) {
> + if (unlikely(cpu->singlestep_enabled)) {
> ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
> }
> #if defined (DO_SINGLE_STEP) && 0
> @@ -11515,7 +11514,7 @@ void gen_intermediate_code(CPUPPCState *env, struct
> TranslationBlock *tb)
> tcg_gen_insn_start(ctx.nip);
> num_insns++;
>
> - if (unlikely(cpu_breakpoint_test(cs, ctx.nip, BP_ANY))) {
> + if (unlikely(cpu_breakpoint_test(cpu, ctx.nip, BP_ANY))) {
> gen_debug_exception(ctxp);
> /* The address covered by the breakpoint must be included in
> [tb->pc, tb->pc + tb->size) in order to for it to be
> @@ -11586,7 +11585,7 @@ void gen_intermediate_code(CPUPPCState *env, struct
> TranslationBlock *tb)
> ctx.exception != POWERPC_EXCP_BRANCH)) {
> gen_exception(ctxp, POWERPC_EXCP_TRACE);
> } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
> - (cs->singlestep_enabled) ||
> + (cpu->singlestep_enabled) ||
> singlestep ||
> num_insns >= max_insns)) {
> /* if we reach a page boundary or are single stepping, stop
> @@ -11606,7 +11605,7 @@ void gen_intermediate_code(CPUPPCState *env, struct
> TranslationBlock *tb)
> if (ctx.exception == POWERPC_EXCP_NONE) {
> gen_goto_tb(&ctx, 0, ctx.nip);
> } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
> - if (unlikely(cs->singlestep_enabled)) {
> + if (unlikely(cpu->singlestep_enabled)) {
> gen_debug_exception(ctxp);
> }
> /* Generate the return instruction */
> @@ -11623,7 +11622,7 @@ void gen_intermediate_code(CPUPPCState *env, struct
> TranslationBlock *tb)
> flags = env->bfd_mach;
> flags |= ctx.le_mode << 16;
> qemu_log("IN: %s\n", lookup_symbol(pc_start));
> - log_target_disas(cs, pc_start, ctx.nip - pc_start, flags);
> + log_target_disas(cpu, pc_start, ctx.nip - pc_start, flags);
> qemu_log("\n");
> }
> #endif
> diff --git a/target-s390x/translate.c b/target-s390x/translate.c
> index c871ef2..9aac7cd 100644
> --- a/target-s390x/translate.c
> +++ b/target-s390x/translate.c
> @@ -5319,10 +5319,9 @@ static ExitStatus translate_one(CPUS390XState *env,
> DisasContext *s)
> return ret;
> }
>
> -void gen_intermediate_code(CPUS390XState *env, struct TranslationBlock *tb)
> +void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb)
> {
> - S390CPU *cpu = s390_env_get_cpu(env);
> - CPUState *cs = CPU(cpu);
> + CPUS390XState *env = cpu->env_ptr;
> DisasContext dc;
> target_ulong pc_start;
> uint64_t next_page_start;
> @@ -5340,7 +5339,7 @@ void gen_intermediate_code(CPUS390XState *env, struct
> TranslationBlock *tb)
> dc.tb = tb;
> dc.pc = pc_start;
> dc.cc_op = CC_OP_DYNAMIC;
> - do_debug = dc.singlestep_enabled = cs->singlestep_enabled;
> + do_debug = dc.singlestep_enabled = cpu->singlestep_enabled;
>
> next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
>
> @@ -5359,7 +5358,7 @@ void gen_intermediate_code(CPUS390XState *env, struct
> TranslationBlock *tb)
> tcg_gen_insn_start(dc.pc, dc.cc_op);
> num_insns++;
>
> - if (unlikely(cpu_breakpoint_test(cs, dc.pc, BP_ANY))) {
> + if (unlikely(cpu_breakpoint_test(cpu, dc.pc, BP_ANY))) {
> status = EXIT_PC_STALE;
> do_debug = true;
> /* The address covered by the breakpoint must be included in
> @@ -5386,7 +5385,7 @@ void gen_intermediate_code(CPUS390XState *env, struct
> TranslationBlock *tb)
> || tcg_op_buf_full()
> || num_insns >= max_insns
> || singlestep
> - || cs->singlestep_enabled)) {
> + || cpu->singlestep_enabled)) {
> status = EXIT_PC_STALE;
> }
> } while (status == NO_EXIT);
> @@ -5425,7 +5424,7 @@ void gen_intermediate_code(CPUS390XState *env, struct
> TranslationBlock *tb)
> #if defined(S390X_DEBUG_DISAS)
> if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
> qemu_log("IN: %s\n", lookup_symbol(pc_start));
> - log_target_disas(cs, pc_start, dc.pc - pc_start, 1);
> + log_target_disas(cpu, pc_start, dc.pc - pc_start, 1);
> qemu_log("\n");
> }
> #endif
> diff --git a/target-sh4/translate.c b/target-sh4/translate.c
> index 7c18968..5c7fa2c 100644
> --- a/target-sh4/translate.c
> +++ b/target-sh4/translate.c
> @@ -1816,10 +1816,9 @@ static void decode_opc(DisasContext * ctx)
> gen_store_flags(ctx->flags);
> }
>
> -void gen_intermediate_code(CPUSH4State * env, struct TranslationBlock *tb)
> +void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb)
> {
> - SuperHCPU *cpu = sh_env_get_cpu(env);
> - CPUState *cs = CPU(cpu);
> + CPUSH4State * env = cpu->env_ptr;
> DisasContext ctx;
> target_ulong pc_start;
> int num_insns;
> @@ -1834,7 +1833,7 @@ void gen_intermediate_code(CPUSH4State * env, struct
> TranslationBlock *tb)
> so assume it is a dynamic branch. */
> ctx.delayed_pc = -1; /* use delayed pc from env pointer */
> ctx.tb = tb;
> - ctx.singlestep_enabled = cs->singlestep_enabled;
> + ctx.singlestep_enabled = cpu->singlestep_enabled;
> ctx.features = env->features;
> ctx.has_movcal = (ctx.flags & TB_FLAG_PENDING_MOVCA);
>
> @@ -1852,7 +1851,7 @@ void gen_intermediate_code(CPUSH4State * env, struct
> TranslationBlock *tb)
> tcg_gen_insn_start(ctx.pc, ctx.flags);
> num_insns++;
>
> - if (unlikely(cpu_breakpoint_test(cs, ctx.pc, BP_ANY))) {
> + if (unlikely(cpu_breakpoint_test(cpu, ctx.pc, BP_ANY))) {
> /* We have hit a breakpoint - make sure PC is up-to-date */
> tcg_gen_movi_i32(cpu_pc, ctx.pc);
> gen_helper_debug(cpu_env);
> @@ -1874,7 +1873,7 @@ void gen_intermediate_code(CPUSH4State * env, struct
> TranslationBlock *tb)
> ctx.pc += 2;
> if ((ctx.pc & (TARGET_PAGE_SIZE - 1)) == 0)
> break;
> - if (cs->singlestep_enabled) {
> + if (cpu->singlestep_enabled) {
> break;
> }
> if (num_insns >= max_insns)
> @@ -1884,7 +1883,7 @@ void gen_intermediate_code(CPUSH4State * env, struct
> TranslationBlock *tb)
> }
> if (tb->cflags & CF_LAST_IO)
> gen_io_end();
> - if (cs->singlestep_enabled) {
> + if (cpu->singlestep_enabled) {
> tcg_gen_movi_i32(cpu_pc, ctx.pc);
> gen_helper_debug(cpu_env);
> } else {
> @@ -1916,7 +1915,7 @@ void gen_intermediate_code(CPUSH4State * env, struct
> TranslationBlock *tb)
> #ifdef DEBUG_DISAS
> if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
> qemu_log("IN:\n"); /* , lookup_symbol(pc_start)); */
> - log_target_disas(cs, pc_start, ctx.pc - pc_start, 0);
> + log_target_disas(cpu, pc_start, ctx.pc - pc_start, 0);
> qemu_log("\n");
> }
> #endif
> diff --git a/target-sparc/translate.c b/target-sparc/translate.c
> index 7998ff5..cc634ce 100644
> --- a/target-sparc/translate.c
> +++ b/target-sparc/translate.c
> @@ -5217,10 +5217,9 @@ static void disas_sparc_insn(DisasContext * dc,
> unsigned int insn)
> }
> }
>
> -void gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb)
> +void gen_intermediate_code(CPUState *cpu, TranslationBlock * tb)
> {
> - SPARCCPU *cpu = sparc_env_get_cpu(env);
> - CPUState *cs = CPU(cpu);
> + CPUSPARCState * env = cpu->env_ptr;
> target_ulong pc_start, last_pc;
> DisasContext dc1, *dc = &dc1;
> int num_insns;
> @@ -5238,7 +5237,7 @@ void gen_intermediate_code(CPUSPARCState * env,
> TranslationBlock * tb)
> dc->def = env->def;
> dc->fpu_enabled = tb_fpu_enabled(tb->flags);
> dc->address_mask_32bit = tb_am_enabled(tb->flags);
> - dc->singlestep = (cs->singlestep_enabled || singlestep);
> + dc->singlestep = (cpu->singlestep_enabled || singlestep);
>
> num_insns = 0;
> max_insns = tb->cflags & CF_COUNT_MASK;
> @@ -5260,7 +5259,7 @@ void gen_intermediate_code(CPUSPARCState * env,
> TranslationBlock * tb)
> num_insns++;
> last_pc = dc->pc;
>
> - if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) {
> + if (unlikely(cpu_breakpoint_test(cpu, dc->pc, BP_ANY))) {
> if (dc->pc != pc_start) {
> save_state(dc);
> }
> @@ -5322,7 +5321,7 @@ void gen_intermediate_code(CPUSPARCState * env,
> TranslationBlock * tb)
> if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
> qemu_log("--------------\n");
> qemu_log("IN: %s\n", lookup_symbol(pc_start));
> - log_target_disas(cs, pc_start, last_pc + 4 - pc_start, 0);
> + log_target_disas(cpu, pc_start, last_pc + 4 - pc_start, 0);
> qemu_log("\n");
> }
> #endif
> diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c
> index 03918eb..afb248d 100644
> --- a/target-tilegx/translate.c
> +++ b/target-tilegx/translate.c
> @@ -2369,12 +2369,11 @@ static void translate_one_bundle(DisasContext *dc,
> uint64_t bundle)
> }
> }
>
> -void gen_intermediate_code(CPUTLGState *env, struct TranslationBlock *tb)
> +void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb)
> {
> - TileGXCPU *cpu = tilegx_env_get_cpu(env);
> + CPUTLGState *env = cpu->env_ptr;
> DisasContext ctx;
> DisasContext *dc = &ctx;
> - CPUState *cs = CPU(cpu);
> uint64_t pc_start = tb->pc;
> uint64_t next_page_start = (pc_start & TARGET_PAGE_MASK) +
> TARGET_PAGE_SIZE;
> int num_insns = 0;
> @@ -2395,7 +2394,7 @@ void gen_intermediate_code(CPUTLGState *env, struct
> TranslationBlock *tb)
> if (!max_insns) {
> max_insns = CF_COUNT_MASK;
> }
> - if (cs->singlestep_enabled || singlestep) {
> + if (cpu->singlestep_enabled || singlestep) {
> max_insns = 1;
> }
> if (max_insns > TCG_MAX_INSNS) {
> diff --git a/target-tricore/translate.c b/target-tricore/translate.c
> index 912bf22..c852ec6 100644
> --- a/target-tricore/translate.c
> +++ b/target-tricore/translate.c
> @@ -8722,10 +8722,9 @@ static void decode_opc(CPUTriCoreState *env,
> DisasContext *ctx, int *is_branch)
> }
> }
>
> -void gen_intermediate_code(CPUTriCoreState *env, struct TranslationBlock *tb)
> +void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb)
> {
> - TriCoreCPU *cpu = tricore_env_get_cpu(env);
> - CPUState *cs = CPU(cpu);
> + CPUTriCoreState *env = cpu->env_ptr;
> DisasContext ctx;
> target_ulong pc_start;
> int num_insns, max_insns;
> @@ -8746,7 +8745,7 @@ void gen_intermediate_code(CPUTriCoreState *env, struct
> TranslationBlock *tb)
> ctx.pc = pc_start;
> ctx.saved_pc = -1;
> ctx.tb = tb;
> - ctx.singlestep_enabled = cs->singlestep_enabled;
> + ctx.singlestep_enabled = cpu->singlestep_enabled;
> ctx.bstate = BS_NONE;
> ctx.mem_idx = cpu_mmu_index(env, false);
>
> @@ -8778,7 +8777,7 @@ void gen_intermediate_code(CPUTriCoreState *env, struct
> TranslationBlock *tb)
> #ifdef DEBUG_DISAS
> if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
> qemu_log("IN: %s\n", lookup_symbol(pc_start));
> - log_target_disas(cs, pc_start, ctx.pc - pc_start, 0);
> + log_target_disas(cpu, pc_start, ctx.pc - pc_start, 0);
> qemu_log("\n");
> }
> #endif
> diff --git a/target-unicore32/translate.c b/target-unicore32/translate.c
> index 39af3af..cbe6bc2 100644
> --- a/target-unicore32/translate.c
> +++ b/target-unicore32/translate.c
> @@ -1861,10 +1861,9 @@ static void disas_uc32_insn(CPUUniCore32State *env,
> DisasContext *s)
> }
>
> /* generate intermediate code for basic block 'tb'. */
> -void gen_intermediate_code(CPUUniCore32State *env, TranslationBlock *tb)
> +void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb)
> {
> - UniCore32CPU *cpu = uc32_env_get_cpu(env);
> - CPUState *cs = CPU(cpu);
> + CPUUniCore32State *env = cpu->env_ptr;
> DisasContext dc1, *dc = &dc1;
> target_ulong pc_start;
> uint32_t next_page_start;
> @@ -1880,7 +1879,7 @@ void gen_intermediate_code(CPUUniCore32State *env,
> TranslationBlock *tb)
>
> dc->is_jmp = DISAS_NEXT;
> dc->pc = pc_start;
> - dc->singlestep_enabled = cs->singlestep_enabled;
> + dc->singlestep_enabled = cpu->singlestep_enabled;
> dc->condjmp = 0;
> cpu_F0s = tcg_temp_new_i32();
> cpu_F1s = tcg_temp_new_i32();
> @@ -1909,7 +1908,7 @@ void gen_intermediate_code(CPUUniCore32State *env,
> TranslationBlock *tb)
> tcg_gen_insn_start(dc->pc);
> num_insns++;
>
> - if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) {
> + if (unlikely(cpu_breakpoint_test(cpu, dc->pc, BP_ANY))) {
> gen_set_pc_im(dc->pc);
> gen_exception(EXCP_DEBUG);
> dc->is_jmp = DISAS_JUMP;
> @@ -1941,7 +1940,7 @@ void gen_intermediate_code(CPUUniCore32State *env,
> TranslationBlock *tb)
> * Also stop translation when a page boundary is reached. This
> * ensures prefetch aborts occur at the right place. */
> } while (!dc->is_jmp && !tcg_op_buf_full() &&
> - !cs->singlestep_enabled &&
> + !cpu->singlestep_enabled &&
> !singlestep &&
> dc->pc < next_page_start &&
> num_insns < max_insns);
> @@ -1950,7 +1949,7 @@ void gen_intermediate_code(CPUUniCore32State *env,
> TranslationBlock *tb)
> if (dc->condjmp) {
> /* FIXME: This can theoretically happen with self-modifying
> code. */
> - cpu_abort(cs, "IO on conditional branch instruction");
> + cpu_abort(cpu, "IO on conditional branch instruction");
> }
> gen_io_end();
> }
> @@ -1958,7 +1957,7 @@ void gen_intermediate_code(CPUUniCore32State *env,
> TranslationBlock *tb)
> /* At this stage dc->condjmp will only be set when the skipped
> instruction was a conditional branch or trap, and the PC has
> already been written. */
> - if (unlikely(cs->singlestep_enabled)) {
> + if (unlikely(cpu->singlestep_enabled)) {
> /* Make sure the pc is updated, and raise a debug exception. */
> if (dc->condjmp) {
> if (dc->is_jmp == DISAS_SYSCALL) {
> @@ -2017,7 +2016,7 @@ done_generating:
> if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
> qemu_log("----------------\n");
> qemu_log("IN: %s\n", lookup_symbol(pc_start));
> - log_target_disas(cs, pc_start, dc->pc - pc_start, 0);
> + log_target_disas(cpu, pc_start, dc->pc - pc_start, 0);
> qemu_log("\n");
> }
> #endif
> diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c
> index 9894488..51803d5 100644
> --- a/target-xtensa/translate.c
> +++ b/target-xtensa/translate.c
> @@ -3031,10 +3031,9 @@ static void gen_ibreak_check(CPUXtensaState *env,
> DisasContext *dc)
> }
> }
>
> -void gen_intermediate_code(CPUXtensaState *env, TranslationBlock *tb)
> +void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb)
> {
> - XtensaCPU *cpu = xtensa_env_get_cpu(env);
> - CPUState *cs = CPU(cpu);
> + CPUXtensaState *env = cpu->env_ptr;
> DisasContext dc;
> int insn_count = 0;
> int max_insns = tb->cflags & CF_COUNT_MASK;
> @@ -3050,7 +3049,7 @@ void gen_intermediate_code(CPUXtensaState *env,
> TranslationBlock *tb)
> }
>
> dc.config = env->config;
> - dc.singlestep_enabled = cs->singlestep_enabled;
> + dc.singlestep_enabled = cpu->singlestep_enabled;
> dc.tb = tb;
> dc.pc = pc_start;
> dc.ring = tb->flags & XTENSA_TBFLAG_RING_MASK;
> @@ -3085,7 +3084,7 @@ void gen_intermediate_code(CPUXtensaState *env,
> TranslationBlock *tb)
>
> ++dc.ccount_delta;
>
> - if (unlikely(cpu_breakpoint_test(cs, dc.pc, BP_ANY))) {
> + if (unlikely(cpu_breakpoint_test(cpu, dc.pc, BP_ANY))) {
> tcg_gen_movi_i32(cpu_pc, dc.pc);
> gen_exception(&dc, EXCP_DEBUG);
> dc.is_jmp = DISAS_UPDATE;
> @@ -3121,7 +3120,7 @@ void gen_intermediate_code(CPUXtensaState *env,
> TranslationBlock *tb)
> if (dc.icount) {
> tcg_gen_mov_i32(cpu_SR[ICOUNT], dc.next_icount);
> }
> - if (cs->singlestep_enabled) {
> + if (cpu->singlestep_enabled) {
> tcg_gen_movi_i32(cpu_pc, dc.pc);
> gen_exception(&dc, EXCP_DEBUG);
> break;
> @@ -3151,7 +3150,7 @@ void gen_intermediate_code(CPUXtensaState *env,
> TranslationBlock *tb)
> if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
> qemu_log("----------------\n");
> qemu_log("IN: %s\n", lookup_symbol(pc_start));
> - log_target_disas(cs, pc_start, dc.pc - pc_start, 0);
> + log_target_disas(cpu, pc_start, dc.pc - pc_start, 0);
> qemu_log("\n");
> }
> #endif
> diff --git a/translate-all.c b/translate-all.c
> index 8329ea6..940652c 100644
> --- a/translate-all.c
> +++ b/translate-all.c
> @@ -1094,7 +1094,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu,
>
> tcg_func_start(&tcg_ctx);
>
> - gen_intermediate_code(env, tb);
> + gen_intermediate_code(cpu, tb);
>
> trace_translate_block(tb, tb->pc, tb->tc_ptr);
>
>
>
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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