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Re: [Qemu-arm] [Qemu-devel] [PATCH v1 1/1] target-arm: A64: Fix decoding
From: |
Edgar E. Iglesias |
Subject: |
Re: [Qemu-arm] [Qemu-devel] [PATCH v1 1/1] target-arm: A64: Fix decoding of iss_sf in disas_ld_lit |
Date: |
Fri, 30 Sep 2016 12:49:09 +0200 |
User-agent: |
Mutt/1.5.24 (2015-08-30) |
On Fri, Sep 30, 2016 at 12:42:27PM +0200, Thomas Huth wrote:
> On 30.09.2016 12:19, Edgar E. Iglesias wrote:
> > From: "Edgar E. Iglesias" <address@hidden>
> >
> > Fix the decoding of iss_sf in disas_ld_lit.
> > The SF (Sixty-Four) field in the ISS (Instruction Specific Syndrome)
> > is a bit that specifies the width of the register that the
> > instruction loads to.
> >
> > If cleared it specifies 32 bits.
> > If set it specifies 64 bits.
> >
> > Signed-off-by: Edgar E. Iglesias <address@hidden>
> > ---
> > target-arm/translate-a64.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
> > index ddf52f5..eae25c3 100644
> > --- a/target-arm/translate-a64.c
> > +++ b/target-arm/translate-a64.c
> > @@ -2025,7 +2025,7 @@ static void disas_ld_lit(DisasContext *s, uint32_t
> > insn)
> > do_fp_ld(s, rt, tcg_addr, size);
> > } else {
> > /* Only unsigned 32bit loads target 32bit registers. */
> > - bool iss_sf = opc == 0 ? 32 : 64;
> > + bool iss_sf = opc == 0 ? false : true;
>
> You could simplify that to:
>
> bool iss_sf = !(opc == 0);
I don't really see how that is simpler/clearer.
I considered:
bool iss_sf = opc != 0;
but felt the expanded one was clearer in particular as a patch for review.
In any case, I have no strong opinion on the syntax.
Cheers,
Edgar
- [Qemu-arm] [PATCH v1 1/1] target-arm: A64: Fix decoding of iss_sf in disas_ld_lit, Edgar E. Iglesias, 2016/09/30
- Re: [Qemu-arm] [Qemu-devel] [PATCH v1 1/1] target-arm: A64: Fix decoding of iss_sf in disas_ld_lit, Thomas Huth, 2016/09/30
- Re: [Qemu-arm] [Qemu-devel] [PATCH v1 1/1] target-arm: A64: Fix decoding of iss_sf in disas_ld_lit,
Edgar E. Iglesias <=
- Re: [Qemu-arm] [Qemu-devel] [PATCH v1 1/1] target-arm: A64: Fix decoding of iss_sf in disas_ld_lit, Peter Maydell, 2016/09/30
- Re: [Qemu-arm] [Qemu-devel] [PATCH v1 1/1] target-arm: A64: Fix decoding of iss_sf in disas_ld_lit, Eric Blake, 2016/09/30
- Re: [Qemu-arm] [Qemu-devel] [PATCH v1 1/1] target-arm: A64: Fix decoding of iss_sf in disas_ld_lit, Edgar Iglesias, 2016/09/30
- Re: [Qemu-arm] [Qemu-devel] [PATCH v1 1/1] target-arm: A64: Fix decoding of iss_sf in disas_ld_lit, Peter Maydell, 2016/09/30
- Re: [Qemu-arm] [Qemu-devel] [PATCH v1 1/1] target-arm: A64: Fix decoding of iss_sf in disas_ld_lit, Edgar Iglesias, 2016/09/30