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[Qemu-arm] [PATCH 08/10] armv7m: Honour CCR.USERSETMPEND
From: |
Peter Maydell |
Subject: |
[Qemu-arm] [PATCH 08/10] armv7m: Honour CCR.USERSETMPEND |
Date: |
Tue, 24 Jan 2017 19:16:18 +0000 |
From: Michael Davidsaver <address@hidden>
The CCR.USERSETMPEND bit has to be set to permit unprivileged code to
write to the Software Triggered Interrupt register; honour this bit
rather than letting any code write to the register.
Signed-off-by: Michael Davidsaver <address@hidden>
[PMM: Tweak commit message, comment, phrasing of condition]
Signed-off-by: Peter Maydell <address@hidden>
---
hw/intc/armv7m_nvic.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index 60e72d7..fe5c303 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -409,7 +409,10 @@ static void nvic_writel(nvic_state *s, uint32_t offset,
uint32_t value)
"NVIC: Aux fault status registers unimplemented\n");
break;
case 0xf00: /* Software Triggered Interrupt Register */
- if ((value & 0x1ff) < s->num_irq) {
+ /* user mode can only write to STIR if CCR.USERSETMPEND permits it */
+ if ((value & 0x1ff) < s->num_irq &&
+ (arm_current_el(&cpu->env) ||
+ (cpu->env.v7m.ccr & R_V7M_CCR_USERSETMPEND_MASK))) {
gic_set_pending_private(&s->gic, 0, value & 0x1ff);
}
break;
--
2.7.4
- [Qemu-arm] [PATCH 00/10] More M profile bugfixes, Peter Maydell, 2017/01/24
- [Qemu-arm] [PATCH 01/10] target/arm: Drop IS_M() macro, Peter Maydell, 2017/01/24
- [Qemu-arm] [PATCH 07/10] armv7m: Report no-coprocessor faults correctly, Peter Maydell, 2017/01/24
- [Qemu-arm] [PATCH 09/10] armv7m: FAULTMASK should be 0 on reset, Peter Maydell, 2017/01/24
- [Qemu-arm] [PATCH 08/10] armv7m: Honour CCR.USERSETMPEND,
Peter Maydell <=
- [Qemu-arm] [PATCH 05/10] armv7m: honour CCR.STACKALIGN on exception entry, Peter Maydell, 2017/01/24
- [Qemu-arm] [PATCH 10/10] armv7m: R14 should reset to 0xffffffff, Peter Maydell, 2017/01/24
- [Qemu-arm] [PATCH 03/10] armv7m: add state for v7M CCR, CFSR, HFSR, DFSR, MMFAR, BFAR, Peter Maydell, 2017/01/24
- [Qemu-arm] [PATCH 04/10] armv7m: implement CCR, CFSR, HFSR, DFSR, BFAR, and MMFAR, Peter Maydell, 2017/01/24