Re: [Qemu-arm] [PATCH v9 25/25] tcg: enable MTTCG by default for ARM on x86 hosts

[Peter Maydell]

On 1 February 2017 at 15:05, Alex Bennée <address@hidden> wrote:
> This enables the multi-threaded system emulation by default for ARMv7
> and ARMv8 guests using the x86_64 TCG backend. This is because on the
> guest side:
>
>   - The ARM translate.c/translate-64.c have been converted to
>     - use MTTCG safe atomic primitives
>     - emit the appropriate barrier ops
>   - The ARM machine has been updated to
>     - hold the BQL when modifying shared cross-vCPU state
>     - defer cpu_reset to async safe work
>
> All the host backends support the barrier and atomic primitives but
> need to provide same-or-better support for normal load/store
> operations.

> diff --git a/cpus.c b/cpus.c
> index e3d9f3fe21..e1b82bcd49 100644
> --- a/cpus.c
> +++ b/cpus.c
> @@ -176,8 +176,8 @@ bool mttcg_enabled;
>
>  static bool check_tcg_memory_orders_compatible(void)
>  {
> -#if defined(TCG_DEFAULT_MO) && defined(TCG_TARGET_DEFAULT_MO)
> -    return (TCG_DEFAULT_MO & ~TCG_TARGET_DEFAULT_MO) == 0;
> +#if defined(TCG_GUEST_DEFAULT_MO) && defined(TCG_TARGET_DEFAULT_MO)
> +    return (TCG_GUEST_DEFAULT_MO & ~TCG_TARGET_DEFAULT_MO) == 0;

This looks like maybe something that should have been squashed
into an earlier part of the patchset?

>  #else
>      return false;
>  #endif
> diff --git a/target/arm/cpu.h b/target/arm/cpu.h
> index a3c4d07817..0ef31db3e0 100644
> --- a/target/arm/cpu.h
> +++ b/target/arm/cpu.h
> @@ -30,6 +30,9 @@
>  #  define TARGET_LONG_BITS 32
>  #endif
>
> +/* ARM processors have a weak memory model */
> +#define TCG_GUEST_DEFAULT_MO      (0)

Do you need the () ?


That said, if Richard is happy with turning this on then
I'm happy to do so.

Acked-by: Peter Maydell <address@hidden>

thanks
-- PMM