[Qemu-arm] [PATCH 2/8] target/arm: optimize smul_dual() and neon_trn_u8() using extract op

[Philippe Mathieu-Daudé]

Applied using Coccinelle script.

Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
---
 target/arm/translate.c | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/target/arm/translate.c b/target/arm/translate.c
index 0b5a0bca06..3230efe1be 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -339,8 +339,7 @@ static void gen_smul_dual(TCGv_i32 a, TCGv_i32 b)
 static void gen_rev16(TCGv_i32 var)
 {
     TCGv_i32 tmp = tcg_temp_new_i32();
-    tcg_gen_shri_i32(tmp, var, 8);
-    tcg_gen_andi_i32(tmp, tmp, 0x00ff00ff);
+    tcg_gen_extract_i32(tmp, var, 8, 0x00ff00ff);
     tcg_gen_shli_i32(var, var, 8);
     tcg_gen_andi_i32(var, var, 0xff00ff00);
     tcg_gen_or_i32(var, var, tmp);
@@ -4700,8 +4699,7 @@ static void gen_neon_trn_u8(TCGv_i32 t0, TCGv_i32 t1)
     tcg_gen_andi_i32(tmp, t1, 0x00ff00ff);
     tcg_gen_or_i32(rd, rd, tmp);
 
-    tcg_gen_shri_i32(t1, t1, 8);
-    tcg_gen_andi_i32(t1, t1, 0x00ff00ff);
+    tcg_gen_extract_i32(t1, t1, 8, 0x00ff00ff);
     tcg_gen_andi_i32(tmp, t0, 0xff00ff00);
     tcg_gen_or_i32(t1, t1, tmp);
     tcg_gen_mov_i32(t0, rd);
-- 
2.11.0