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[Qemu-arm] [PATCH v5 03/10] target/arm: optimize aarch64 rev16() using e


From: Philippe Mathieu-Daudé
Subject: [Qemu-arm] [PATCH v5 03/10] target/arm: optimize aarch64 rev16() using extract op
Date: Tue, 18 Jul 2017 01:55:33 -0300

Aurelien Jarno denoted this function could be implemented more effectively using
the aarch32 rev16() pattern.
  [http://lists.nongnu.org/archive/html/qemu-devel/2017-05/msg03180.html]

Done with the Coccinelle semantic patch from commit 58daf05d07dd
    (see scripts/coccinelle/tcg_gen_extract.cocci)

Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
---
Richard: maybe you need to update 58daf05d07dd to your commit...

 target/arm/translate-a64.c | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index e55547d95d..8ade865481 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -4046,14 +4046,12 @@ static void handle_rev16(DisasContext *s, unsigned int 
sf,
     tcg_gen_andi_i64(tcg_tmp, tcg_rn, 0xffff);
     tcg_gen_bswap16_i64(tcg_rd, tcg_tmp);
 
-    tcg_gen_shri_i64(tcg_tmp, tcg_rn, 16);
-    tcg_gen_andi_i64(tcg_tmp, tcg_tmp, 0xffff);
+    tcg_gen_extract_i64(tcg_tmp, tcg_rn, 16, 16);
     tcg_gen_bswap16_i64(tcg_tmp, tcg_tmp);
     tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_tmp, 16, 16);
 
     if (sf) {
-        tcg_gen_shri_i64(tcg_tmp, tcg_rn, 32);
-        tcg_gen_andi_i64(tcg_tmp, tcg_tmp, 0xffff);
+        tcg_gen_extract_i64(tcg_tmp, tcg_rn, 32, 16);
         tcg_gen_bswap16_i64(tcg_tmp, tcg_tmp);
         tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_tmp, 32, 16);
 
-- 
2.13.2




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