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Re: [Qemu-arm] [RFC PATCH for 2.11 12/23] target/arm/translate-a64.c: ad
From: |
Alex Bennée |
Subject: |
Re: [Qemu-arm] [RFC PATCH for 2.11 12/23] target/arm/translate-a64.c: add FP16 FAGCT to AdvSIMD 3 Same |
Date: |
Fri, 21 Jul 2017 10:56:04 +0100 |
User-agent: |
mu4e 0.9.19; emacs 25.2.50.3 |
Richard Henderson <address@hidden> writes:
> On 07/20/2017 05:04 AM, Alex Bennée wrote:
>> +static softfloat_flags softfloat_mapping_table[] = {
>> + { float_flag_inexact , softfloat_flag_inexact },
>> + { float_flag_underflow, softfloat_flag_underflow },
>> + { float_flag_overflow , softfloat_flag_overflow },
>> + { float_flag_invalid , softfloat_flag_invalid },
>> +};
>> +/* FIXME: 2a has no infinite flag */
>> +
>> +static uint8_t sync_softfloat_flags_from_2a(float_status *flags2a)
>> +{
>> + uint8_t flags = flags2a->float_exception_flags;
>> + int i;
>> + if (flags) {
>> + for (i = 0; i < ARRAY_SIZE(softfloat_mapping_table); i++) {
>> + struct softfloat_flags *map = &softfloat_mapping_table[i];
>> + if (flags & map->float2a_flag) {
>> + softfloat_raiseFlags(map->float3c_flag);
>> + }
>> + }
>> + } else {
>> + softfloat_exceptionFlags = 0;
>> + }
>> +
>> + return softfloat_exceptionFlags;
>> +}
>> +
>
> For conversions like this IMO it's better to make the compiler do the
> work. C.f. target/alpha/fpu_helper.c and CONVERT_BIT.
Cool, I'll look at that.
> BTW, I think these TLS variables that softfloat3a are using are going
> to be a real problem. It's one thing to do it temporarily like you
> are here, coordinating between 2a and 3c, but later, when the front
> end is fully converted? That's just nonsense.
Wouldn't the other option to be to drop float_status out of the guests
CPUEnv and grab it from the TLS variable instead? Of course all guests
would need to be MTTCG enabled for that to work.
> Is it going to be worthwhile to significantly hack up the incoming sources?
>
> If so, then we might do something like this: Given a 3c function foo,
>
> T foo_st(T, T, float3a_status *) { ... }
> T foo(T x, T y) { return foo_st(x, y, &tls_status); }
>
> And of course pack all of the relevant state into a struct then
>
> #define softfloat_exceptionFlags tls_status.exceptionflags
>
> etc, instead of having individual tls variables. This feels like
> something that we could push back upstream, assuming that upstream is
> active.
Peter has found what might be an upstream source repository so we can
certainly look at that.
--
Alex Bennée
- Re: [Qemu-arm] [RFC PATCH for 2.11 05/23] softfloat3c: initial build machinery, (continued)
[Qemu-arm] [RFC PATCH for 2.11 08/23] target-aarch64: enable SoftFloat3 build for FP16, Alex Bennée, 2017/07/20
[Qemu-arm] [RFC PATCH for 2.11 09/23] arm: introduce ARM_V8_FP16 feature bit, Alex Bennée, 2017/07/20
[Qemu-arm] [RFC PATCH for 2.11 11/23] target/arm/translate-a64.c: AdvSIMD scalar 3 Same FP16 initial decode, Alex Bennée, 2017/07/20
[Qemu-arm] [RFC PATCH for 2.11 13/23] target/arm/translate-a64.c: add FP16 FADD to AdvSIMD 3 Same, Alex Bennée, 2017/07/20
[Qemu-arm] [RFC PATCH for 2.11 12/23] target/arm/translate-a64.c: add FP16 FAGCT to AdvSIMD 3 Same, Alex Bennée, 2017/07/20
Re: [Qemu-arm] [RFC PATCH for 2.11 12/23] target/arm/translate-a64.c: add FP16 FAGCT to AdvSIMD 3 Same, Alex Bennée, 2017/07/28
Re: [Qemu-arm] [RFC PATCH for 2.11 12/23] target/arm/translate-a64.c: add FP16 FAGCT to AdvSIMD 3 Same, Richard Henderson, 2017/07/28
[Qemu-arm] [RFC PATCH for 2.11 17/23] fpu/softfloat2a: implement propagateFloat16NaN, Alex Bennée, 2017/07/20
[Qemu-arm] [RFC PATCH for 2.11 04/23] softfloat3c: fixup include paths, Alex Bennée, 2017/07/20
[Qemu-arm] [RFC PATCH for 2.11 15/23] target/arm/translate-a64.c: AdvSIMD scalar 2 register misc decode, Alex Bennée, 2017/07/20