Re: [Qemu-arm] [RFC PATCH 17/30] target/arm/translate-a64.c: add FP16 FMULX

[Richard Henderson]

On 10/13/2017 09:24 AM, Alex Bennée wrote:
> --- a/target/arm/translate-a64.c
> +++ b/target/arm/translate-a64.c
> @@ -10648,7 +10648,7 @@ static void disas_simd_indexed(DisasContext *s, 
> uint32_t insn)
>          }
>          /* fall through */
>      case 0x9: /* FMUL, FMULX */
> -        if (!extract32(size, 1, 1)) {
> +        if (!extract32(size, 1, 1) && !arm_dc_feature(s, 
> ARM_FEATURE_V8_FP16)) {
>              unallocated_encoding(s);
>              return;
>          }

This isn't quite right --

  00 = fp16
  10 = fp32
  11 = fp64

You still need to diagnose 01.

> @@ -10805,10 +10817,23 @@ static void disas_simd_indexed(DisasContext *s, 
> uint32_t insn)
>                  gen_helper_vfp_muladds(tcg_res, tcg_op, tcg_idx, tcg_res, 
> fpst);
>                  break;
>              case 0x9: /* FMUL, FMULX */
> -                if (u) {
> -                    gen_helper_vfp_mulxs(tcg_res, tcg_op, tcg_idx, fpst);
> -                } else {
> -                    gen_helper_vfp_muls(tcg_res, tcg_op, tcg_idx, fpst);
> +                switch (size) {
> +                case 1:

MO_* here, since you converted to them above.


r~