Re: [Qemu-arm] [Qemu-trivial] [PATCH] hw/timer/armv7m_systick: Fix default system_clock_scale. Resolves SIGFPE divide by zero.

[Domen Puncer Kugler]

On 2 November 2017 at 03:31, Philippe Mathieu-Daudé <address@hidden> wrote:
> Please have a look at the Contribute/SubmitAPatch guidelines for QEMU,
> in particular about CC'ing the maintainers so your patch won't get lost:

Apologies for that.
Thanks

>> Netduino platform code does not provide a way to set
>> system_clock_scale, so it remains 0.
>> This causes a divide by zero, when emulated code asks systick for
>> current timer value:
>>     (s->tick - (t + 1)) / systick_scale(s)) + 1;
>> Patch fixes this by providing a default value.
>
> See the thread around this reply:
> http://lists.nongnu.org/archive/html/qemu-devel/2017-06/msg06678.html

I see. Personally, I don't really mind waiting for proper support.
It's a solved problem for me now (SYSTICK_CLKSOURCE = 0 [external] for
qemu target), but I suspect it might also bite someone else.
Are there any downsides to the simple fix?

For background:

arm arm v7m says:
[2] R/W CLKSOURCE 0: clock source is (optional) external reference clock
                  1: core clock used for SysTick
                  If no external clock provided, this bit will read as
1 and ignore writes.
// note that the optional case actually works fine with qemu, core
clock case doesn't

stm32 docs say (my target is stm32/netduino2):
The RCC feeds the external clock of the Cortex System Timer (SysTick)
with the AHB clock (HCLK) divided by 8. The SysTick can work either
with this clock or with the Cortex clock (HCLK), configurable in the
SysTick control and status register.
The timer clock frequencies are automatically set by hardware.