[Qemu-arm] [PATCH] arm/translate-a64: mark path as unreachable to eliminate warning

[Emilio G. Cota]

Fixes the following warning when compiling with gcc 5.4.0 with -O1
optimizations and --enable-debug:

target/arm/translate-a64.c: In function ‘aarch64_tr_translate_insn’:
target/arm/translate-a64.c:2361:8: error: ‘post_index’ may be used 
uninitialized in this function [-Werror=maybe-uninitialized]
     if (!post_index) {
        ^
target/arm/translate-a64.c:2307:10: note: ‘post_index’ was declared here
     bool post_index;
          ^
target/arm/translate-a64.c:2386:8: error: ‘writeback’ may be used uninitialized 
in this function [-Werror=maybe-uninitialized]
     if (writeback) {
        ^
target/arm/translate-a64.c:2308:10: note: ‘writeback’ was declared here
     bool writeback;
          ^

Note that idx comes from selecting 2 bits, and therefore its value
can be at most 3.

Signed-off-by: Emilio G. Cota <address@hidden>
---
 target/arm/translate-a64.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index caca05a..625ef2d 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -2340,28 +2340,30 @@ static void disas_ldst_reg_imm9(DisasContext *s, 
uint32_t insn,
     switch (idx) {
     case 0:
     case 2:
         post_index = false;
         writeback = false;
         break;
     case 1:
         post_index = true;
         writeback = true;
         break;
     case 3:
         post_index = false;
         writeback = true;
         break;
+    default:
+        g_assert_not_reached();
     }
 
     if (rn == 31) {
         gen_check_sp_alignment(s);
     }
     tcg_addr = read_cpu_reg_sp(s, rn, 1);
 
     if (!post_index) {
         tcg_gen_addi_i64(tcg_addr, tcg_addr, imm9);
     }
 
     if (is_vector) {
         if (is_store) {
             do_fp_st(s, rt, tcg_addr, size);
-- 
2.7.4