Re: [Qemu-arm] [PATCH v5 0/8] aspeed: add a witherspoon-bmc machine

[Peter Maydell]

On 29 November 2017 at 09:58, Cédric Le Goater <address@hidden> wrote:
> On 10/19/2017 05:12 PM, Cédric Le Goater wrote:
>>  - introduce a dummy ROM device to catch invalid writes
>>  - removed 'ignore_memory_transaction_failures' on all Aspeed machines
>
> So that was a bad idea because old firwmares run load/store loops
> beyond the address space to guess how much RAM the SoC has.
>
> I am wondering if it is possible to model the same behavior with
> a MMIO region (of a correct size depending on the max ram size of
> the SoC) and mapped beyond the RAM region to catch such accesses
> and keep 'ignore_memory_transaction_failures' to false.

Yeah, if the hardware genuinely ignores accesses to a particular
region of the address space then you can model this with an
appropriate background memory region. You just need to figure
out what range of the address space it should apply to...

thanks
-- PMM